Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1998-10-05
2001-10-16
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
Reexamination Certificate
active
06303458
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to the fabrication of alignment makes in a semiconductor device and, more particularly, to a method involving shallow trench isolation (STI) using a special mask to clear an insulating layer from over an alignment pattern in a semiconductor substrate and to clear the insulating layer from over Active areas in device areas.
2) Description of the Prior Art
As the level of integration in semiconductor devices has increased, device sizes have become smaller. Along with the trend, device isolation structures for electrical isolation between adjacent devices have also become smaller.
For STI structures, trenches are formed into a semiconductor substrate. Thereafter, the trenches are filled with an insulating material, like an oxide film, to a thickness sufficient to bury the trenches. Subsequently, the insulating materials etched back by a chemical mechanical polishing (CMP) method until the surface of an adjacent active region is exposed, thereby planarizing the whole surface of the semiconductor substrate having the trenches formed thereon. Thus, the device isolation structure is completed. The STI method is free of bird's beaks and has an advantage over the LOCOS structures with respect to minimization of isolation spacing. It possesses, however, a distinct drawback that an alignment pattern necessary for subsequent photolithography steps is not obtained, since not enough step is created on the surface of the semiconductor substrate in the STI structure. Conventionally, when a laser is projected from an aligner of a stepper and reflected on an alignment marks formed on the semiconductor substrate, an interference pattern formed due to the irregularities of the alignment mark pattern. The interference pattern is recognized in a detector, the direction and position of the semiconductor substrate are detected, and then the semiconductor substrate and equipment are adjusted in accordance with the detected direction and position of the semiconductor substrate, thereby performing alignment. However, in the STI, a device isolation oxide film is formed by etching back through using the chemical-mechanical polish method or the like, thus providing a planar semiconductor substrate without any step between the device formation area and the device isolation area.
When an opaque film like a tungsten silicide, used as a gate electrode material, is formed on such a planar surface, an interference pattern due to reflection will not be formed. The alignment of the photolithographic equipment, therefore, is practically difficult to perform.
FIG. 8
shows a top plan view of a preferred location of an alignment mark area
14
between prime dies
17
in a kerf
19
on a substrate
10
.
A method for forming alignment mark patterns in a shallow trench isolation (STI) structure using a special mask and conventional technology will now be described in detail, referring to the attached drawings.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,700,732(Jost) shows a method of forming alignment marks in substrates using varying etch depths.
U.S. Pat. No. 5,401,691(Caldwell) shows a method of forming Alignment marks in layers using inverse frames.
U.S. Pat. No. 5,578,519(Cho) shows a method of forming an alignment mark using an STI process. U.S. Pat. No. 5,316,966(Van Der Plas et al. ) shows a method of forming alignment marks using STI processes.
U.S. Pat. No. 5,369,050(Kawai) shows another method of forming alignment marks in isolation areas.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for removing insulating layers from over alignment marks using a mask that reduces the number of masking steps.
It is an object of the present invention to provide a method for removing insulating layers from over alignment marks using a mask that also opens die area with some generation rule to improve CMP process.
It is an object of the present invention to provide a method using a novel mask for removing insulating layers from over alignment marks and for removing insulating layers from over active area (active area reverse mask) for chemical-mechanical polish processes.
It is an object of the invention to use provide a first mask
60
that combines (1) active reverse mask (that removes oxide from the active areas
44
in device areas
12
) and (2) an alignment mark open mask (that removes oxide
50
from over the alignment mark areas
14
).
To accomplish the above objectives, the present invention provides a method of fabrication an alignment mark in a semiconductor device. The method uses one mask
60
to that has two functions (1) a reverse active areas mask to remove the oxide from over active areas in the device areas
12
and (2) an alignment mark open mask
60
that removes the oxide from over the alignment mark area
14
. The mask improves chemical-mechanical polish performance in the cell areas by removing the oxide over the active areas
44
. Another key feature of the invention is the spacing of the alignment mark trenches
40
that ensure that the step distance
12
between the top of the second insulating layer in the alignment mark trench
40
and the top surface of the substrate
10
is greater than 2000 Å. This insures that the alignment mark are readable. The invention's spaces specifications are as follows: the alignment mark trenches have a width
40
W greater than about 2 &mgr;m, and the active areas
41
in the alignment mark area
14
having a width
41
W greater than 3 &mgr;m.
The method includes the following steps. We form a first insulating film pattern
30
for defining STI regions in a cell array area
12
and defining alignment mark trenches regions in an alignment mark area
14
on a semiconductor substrate
10
. Next STI trenches
42
are formed in the STI regions and alignment mark trenches
30
are formed in the alignment mark area
14
, using the first insulating film pattern
30
as a mask. The STI trenches
42
and alignment mark trenches
40
are formed defining active areas
44
41
. The alignment mark trenches
40
have a width
40
W greater than about 2 &mgr;m, and the active areas
41
in the alignment mark area
14
having a width greater than 3 &mgr;m.
Then, we form a second insulating film
40
on the whole surface of the semiconductor substrate, while filling the STI trenches
30
and the alignment mark trenches
40
;
A important first mask (L
11
mask) is formed covering the STI regions in the cell array area and having an opening over the alignment mark area
14
.
We etch the second insulating film
40
formed on the active regions
44
41
of the cell array area and etch the second insulating film
40
formed on the alignment mark area, to a predetermined thickness.
Subsequently, we chemical-mechanical polish the second insulating layer to expose the first insulating film pattern leaving portions of the second insulating layer in the alignment mark trenches and STI trenches. A step distance
12
between the top of the second insulating layer in the alignment mark trench and the top surface of the substrate is greater than 2000 Å. Lastly, the first insulating film pattern is removed.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 5316966 (1994-05-01), Van Der Plas et al.
patent: 5369050 (1994-11-01), Kawai
patent: 5401691 (1995-03-01), Caldwell
patent: 5578519 (1996-11-01), Cho
patent: 5700732 (1997-12-01),
Gan Chock Hing
Qian Gang
Zhang Yunqiang
Chartered Semiconductor Manufacturing Ltd.
Mulpuri Savitri
Pike Rosemary L. S.
Saile George O.
Stoffel William J.
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