Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2001-01-30
2002-08-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S975000, C438S427000, C257S797000
Reexamination Certificate
active
06440816
ABSTRACT:
TECHNICAL FIELD
This invention relates to the field of lithography and in particular, to a method of fabrication.
BACKGROUND ART
FIG. 1
schematically depicts a Scattering with Angular Limitation in Projection Electron Lithography (SCALPEL) process. In general, the SCALPEL approach employs the principle of electron scattering to delineate circuit patterns on substrates. A mask
2
is used to shape an electron beam source. Mask
2
includes electron transmissive regions
22
and
24
having different electron scattering properties. Region
22
is a pattern of high electron scattering material, examples of which include high atomic number metals such as gold and tungsten. Region
24
is a low electron scattering material, for example, a low atomic number element or compound, such as silicon or silicon nitride formed into a membrane.
As electron beam
1
traverses the mask
2
, electrons are scattered, the amount and angle of scattering being a function of the atomic number of the constituent atoms in the material. As a result of the differential scattering properties of the mask
2
, an angular distribution of electrons is formed at the exit surface of the mask
2
. Those electrons
3
having passed through patterned region
22
of high atomic number material are generally scattered to a higher angle than those electrons
4
which passed only through the low atomic number membrane region
24
.
The scattered electrons
3
and
4
pass into projection lens system
30
, which demagnifies the image formed by the scattered electrons. In the back focal plane of the projecting lens system, the electrons are distributed by their angle of scatter. A filter
40
having an aperture
42
is placed in the back focal plane to angularly select electrons, which will form the ultimate image. If aperture
42
is sufficiently small and on the focal axis, only those electrons scattered through small angels will contribute to the final image
52
on substrate
50
. The electrons scattered through small angles
3
, i.e., electrons which passed through the low atomic number membrane regions
24
, are the electrons which interact with a substrate material, such as a resist, to create a latent image. For a given mask and optical system, the contrast in the image is determined by the size of the angularly limiting aperture. SCALPEL lithography is further described in Berger et al., J. Vac. Sci. Technol., B9, November/December 1991, pp. 2996-1999 and U.S. Pat. Nos. 5,079,112 and 5,130,213, the entire contents of which are incorporated by reference herein.
As described above, device fabrication technology is based on the use of lithography (SCALPEL being one example) to create the features and patterns that make up an integrated circuit. Because many patterns may be combined to form an integrated circuit, the substrate on which the device is formed should be precisely aligned with the lithographic apparatus to ensure that the pattern being introduced aligns properly with the other patterns already formed on the substrate as well as those patterns that are formed subsequently on the substrate. Alignment marks are typically formed on the substrate to assist in the orientation of the substrate, the mask pattern that is used to pattern the radiation introduced onto the substrate, and the optics of the lithographic apparatus.
The detectability of the alignment marks depends upon the mark layout, the material used to fabricate the mark, the topography of the mark, and the operating conditions during mark detection.
Alignment mark detection is affected by many factors including mark geometry, signal-to-noise ratio and detector efficiency.
In U.S. Pat. No. 5,824,441, the entire contents of which is incorporated by reference herein, a mask and a substrate are aligned using topographic alignment marks in which the material and configuration thereof have been selected to obtain a desirable backscattered electron (BSE) signal contrast between an aligned and a non-aligned state (hereinafter referred to as BSE contrast). The technique may be used in a lithographic process for device fabrication in which an electron beam generator is the source of the exposing energy. Examples of such processes include projection electron beam lithography, shaped beam lithography, and direct write electron beam lithography.
In U. S. Pat. No. 5,824,441, the BSE contrast is a function of the alignment mark geometry, the energy of the incident electron beam, the position of the electron detector relative to the alignment marks on the wafer, and the material in which the alignment marks are formed.
The dimensions of the alignment mark should also be selected to be compatible with the dimensions of the devices to be fabricated by the process in which the alignment marks are used. That is, if the critical dimension of the devices being fabricated is 0.1 &mgr;m, then it is advantageous if the width of the alignment marks features are 0.1 &mgr;m or larger. The detectable signal amplitude (or S/N) as it relates to the area of the mark determines the practical lower limit. The available area between chips (Kerf) on the wafer determines the practical upper limit. The scanning ability of the tool is a practical upper limit on the width of the alignment mark.
As set forth above, alignment marks are introduced into the substrate, typically a silicon wafer or a layer of material overlying a silicon wafer which is commonly used in semiconductor device fabrication, using lithographic techniques well known to one skilled in the art.
As noted in Farrow, R., et al., “Mark topography for alignment and registration in projection electron lithography,”
SPIE
, vol. 2723, pp. 143-149 (March 1996), which is hereby incorporated by reference, a wet etching expedient such as potassium hydroxide is useful to form V-groove alignment marks in a silicon wafer. V-grooves may be formed using e-beam lithography. Trench-shaped alignment marks may be formed using a plasma etch. An alignment mark configuration is selected that is formed by an expedient that is compatible with the overall process for device fabrication.
An issue for process integration of a SCALPEL system is alignment mark detection on integrated circuit process levels that provide minimal backscattered electron (BSE) signal contrast. This is analogous to weak alignment signals in optical lithography but may occur at different levels than for e-beam lithography. Depending on the oxide process, detecting alignment mark signals from thin oxide levels (TOX) (active area) can be challenging for both optical and e-beam lithography. A LOCOS (local oxidation of silicon) process leaves SiO
2
features that have topography (illustrated in
FIG. 2
a
), and provides a suitable alignment mark for traditional optical lithography. Gate alignment to TOX is made more difficult for an optical stepper when shallow trench isolation (STI) is used since a chemical mechanical polish (CMP) usually follows STI. As illustrated in
FIG. 2
b
, CMP leaves little or no topography on the substrate surface. SiO
2
on Si as an alignment mark material is not preferred for e-beam lithography at 100 keV because the BSE contrast (between the SiO
2
alignment marks and the surrounding Si) is minimal with the layer thickness' (i.e., 10-20 nm) that are typically used in CMOS processing. For features with a low aspect ratio (a ratio of height to depth) less than 0.5), the BSE contrast at 100 keV is generally not from topography and is process independent.
An exemplary alignment mark fabrication process is shown in
FIGS. 3
a
-
3
f
. The Si wafer
10
has <100> orientation and a thickness of 200 mm. 150 Å of SiO
2
(layer
12
) and 3200 Å of SiN
x
(layer
14
) are deposited on the Si wafer
10
as shown in
FIG. 3
a
. Resist is applied and photolithography is performed using a mask to form a SCALPEL alignment mark as shown in
FIG. 3
b
. The feature sizes in the mark patterns range from 0.5 to 2.5 &mgr;m. After pattern transfer into the SiO
2
/SiN
x
layer
12
/
14
, the wafer
10
is etched to form trenches
16
in the Si a
Farrow Reginald Conway
Kizilyalli Isik C.
Agere Systems Guardian Corp.
Harness & Dickey & Pierce P.L.C.
Kennedy Jennifer M.
Niebling John F.
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