Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Patent
1997-09-29
1999-01-26
Bowers, Charles
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
438462, H01L 2176
Patent
active
058638253
ABSTRACT:
A method of providing etched alignment marks on a semiconductor workpiece that has a substantially planar surface, such as one that has been polished, for supporting accurate alignment of the workpiece in subsequent process operations. The surface of the semiconductor workpiece includes two layers of materials that abut at the workpiece surface. For example, the workpiece may include a layer of insulative material such as silicon dioxide forming several vias and a layer of conductive material such as tungsten forming plugs in the vias. The method includes etching the substantially planar surface to reduce a height of one of the materials below the height of the other material. For example, the tungstein plugs can be etched to a height that is below the height of the surrounding silicon dioxide. The location where the silicon dioxide abuts the tungsten produces a small bump. This bump then serves as an alignment mark for subsequent operations. Furthermore, such subsequent operations will replicate, and/or enhance, the topographical distinction of the alignment mark.
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Dou Shumay
Hwan Marilyn
Lee Dawn
Osugi Richard
Pasch Nicholas F.
Bowers Charles
LSI Logic Corporation
Taylor John P.
Thompson Craig
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