Alignment accuracy check pattern

Details Alignment accuracy check pattern Alignment accuracy check pattern

1996-05-16

1997-03-25

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

257758, 257765, 257740, 257774, H01L 2348, H01L 2711, H01L 2946

Patent

active

056147678

ABSTRACT:
An alignment accuracy check pattern includes a contact hole formed in an insulating film on a major surface of a semiconductor substrate in a region different from an element region, and a photoresist for patterning which is formed in at least part of the contact hole. A wiring layer is formed under the insulating film, and another insulating film is formed under the wiring layer.

REFERENCES:
patent: 4800176 (1989-01-01), Kakumu et al.
patent: 5103287 (1992-04-01), Mase et al.
patent: 5184205 (1993-02-01), Shibata
patent: 5308682 (1994-05-01), Morikawa
patent: 5323047 (1994-06-01), Nguyen
patent: 5331170 (1994-07-01), Hayashi et al.
patent: 5414297 (1995-05-01), Morita et al.

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