Optics: measuring and testing – By alignment in lateral direction – With registration indicia
Reexamination Certificate
1999-06-11
2004-03-30
Smith, Zandra V. (Department: 2877)
Optics: measuring and testing
By alignment in lateral direction
With registration indicia
C355S055000, C355S053000, C250S548000
Reexamination Certificate
active
06714302
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an aligning method and an aligner, and, more particularly, to an aligning method and an aligner for exposing a wafer to a fine circuit pattern. The aligning method and the aligner find applications in the manufacture of a diversity of devices including semiconductor chips such as ICs and LSIs, display devices such as liquid-crystal panels, detector devices such magnetic heads, and image pickup devices such as CCDs.
2. Description of the Related Art
A projection aligning method and a projection aligner have been conventionally used when devices such as ICs, LSIs, and liquid-crystal panels are manufactured using photolithographic techniques. Through its projection optical system, the projection aligner transfers a circuit pattern of a photo mask or reticle (hereinafter simply referred to as a “mask”) to a photosensitive-agent-coated substrate being exposed, such as a silicon wafer or glass substrate (hereinafter referred to as a “wafer”) on which a photoresist or the like is applied.
As the degree of integration of the devices advances, the resolution requirement for a pattern transferred to a wafer becomes finer, and the area requirement per chip on the wafer increases. Many attempts have been made to meet these ever-increasing requirements.
Available as a technique to increase the resolution is a multiple exposure technique in which a wafer is exposed to a plurality of patterns in an overlapped manner and a portion of the wafer, in which the amount of exposure exceeds the threshold of a resist, is developed. Also available as a technique to enlarge the exposure area is a stitching exposure technique, in which a plurality of patterns are stitched into a wide area for exposure.
In both the multiple exposure technique and the stitching exposure technique, a plurality of exposures are made for the production of a single chip pattern in connection with one layer of a wafer. As the exposure is repeated, the time required to interchange masks and to move the wafer increases, presenting difficulty in improving the throughput (i.e., the output of substrates per unit time) of the aligner.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an aligning method and an aligner, which are of great use and result in an improved overall throughput in the exposure of a wafer to a plurality of mask patterns. It is another object of the present invention to provide an aligning method and an aligner, which present a fine pattern resolution and a large exposure area, compared to the conventional art, and result in improved throughput. It is yet another object of the present invention to provide a device manufacturing method, based on the aligning method and the aligner of the present invention, for permitting, to be manufactured at a low cost and a high yield, a device having a pattern with a high degree of integration.
In a preferred embodiment of the aligning method of the present invention, a wafer having a plurality of areas is exposed to a plurality of mask patterns with one mask pattern being interchanged with a next mask pattern to perform the exposure on a plurality of wafers with one wafer being replaced with a next wafer. The next wafer is exposed to the one mask pattern being used immediately prior to a replacement, when the one wafer is replaced with the next wafer. An area of the one wafer last exposed to the one mask pattern is first exposed to the next mask pattern, when the one mask pattern is interchanged with the next mask pattern.
A device manufacturing method of the present invention includes the steps of exposing a wafer according to the above aligning method, and developing the wafer subsequent to the exposure.
In a preferred embodiment of the present invention, the aligner includes a mask stage for holding a mask, a wafer stage for holding a wafer, and exposure means for illuminating the mask to expose the wafer. The exposure means exposes a plurality of areas of the wafer to a plurality of masks, with one mask being interchanged with a next mask, to perform the exposure on a plurality of wafers, with one wafer being replaced with a next wafer. When the next wafer on the wafer stage is exposed to the mask, subsequent to the exposure of the one wafer, the next wafer is first exposed to the mask held by the mask stage.
In another preferred embodiment of the present invention, the aligner includes a mask stage for holding a mask, a wafer stage for holding a wafer, and exposure means for illuminating the mask to expose the wafer. The exposure means exposes a plurality of areas of the wafer to a plurality of masks, with one mask being interchanged with a next mask. When one wafer is exposed to the next mask, subsequent to the exposure of the one wafer to the one mask, a last exposed area of the one wafer is first exposed to the next mask.
REFERENCES:
patent: 4708466 (1987-11-01), Isohata et al.
patent: 4881100 (1989-11-01), Nakai et al.
patent: 5434026 (1995-07-01), Takatsu et al.
patent: 6327022 (2001-12-01), Nishi
patent: 4-267537 (1992-09-01), None
Suzuki Akiyoshi
Yoshii Minoru
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Smith Zandra V.
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