Aliasing nodes to improve the code generated by a circuit compil

Details Aliasing nodes to improve the code generated by a circuit compil Aliasing nodes to improve the code generated by a circuit compil

1996-12-05

1999-04-06

Teska, Kevin J.

Boots, shoes, and leggings

395705, 395708, 395710, 364578, 364489, G06F 9455

Patent

active

058929401

ABSTRACT:
Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached. A scoring function is used to prioritize which logic gate and which nodes are to be selected for code generation. Tri-state buffers are simulated using boolean operations. Drive-fight checking is also accomplished using boolean operations.

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