Algorithmic analog-to-digital converter with reduced differentia

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

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341118, H03M 138

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active

060973269

ABSTRACT:
An analog to digital converter section for use in an analog to digital converter which includes a converter stage which produces a digital and an residue output. The residue output is applied to an over-range stage which produces a second residue output equal to the first residue output reduced in magnitude by the magnitude of a reference voltage. The over-range stage is capable of operating with a relatively high feedback factor to increase operating speed and with commutated feedback-capacitor switching to reduce differential non-linearity errors.

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IEEE Transactions on Circuits and Systems--II: Analog and Digital Signal Processing, vol. 42, No. 7, Jul., 1995, A Pipelined A/D Conversion Technique with Near-Inherent Monotonicity, Paul C. Yu and Hae-Seung Lee; pp. 500-502.
IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec., 1996, A 2.5- V, 12-b, 5-MSample/s Pipelined CMOS ADC, Paul C. Yu, Member, IEEE, and Hae-Seung Lee, Fellow, IEEE; pp. 1854-1861.

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