Algorithmic analog-to-digital converter

Coded data generation or conversion – Converter calibration or testing

Reexamination Certificate

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Reexamination Certificate

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07847713

ABSTRACT:
Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution.

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Young-Jae Cho et at., “A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications,” IEEE 2006 Custom Intergrated Circuits Conference, 2006, pp. 497-500.

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