Algorithmic A/D converter with digitally calibrated output

Details Algorithmic A/D converter with digitally calibrated output Algorithmic A/D converter with digitally calibrated output

1995-03-28

1996-04-23

Williams, Howard L.

Coded data generation or conversion

Converter calibration or testing

341163, 341172, H03M 110

Patent

active

055107893

ABSTRACT:
A multistage pipelined algorithmic A/D converter digitally calibrated to avoid errors due to charge injection, offset and capacitor mismatch. To perform this calibration, measurements are made at the converter to determine the degree of capacitor mismatch for each stage to be calibrated. In the embodiment disclosed, only one stage is calibrated. The remaining stages of the converter are employed to develop the digital calibration data for the stage being measured. This calibration data is stored in a memory forming part of the converter. The stored data is thereafter used during each conversion to cancel the errors due to capacitor mismatch.

REFERENCES:
patent: 4399426 (1983-08-01), Tan
patent: 4415882 (1983-11-01), Akazawa et al.
patent: 4745394 (1988-05-01), Cornett
patent: 4748440 (1988-05-01), Kobayashi
patent: 4760376 (1988-07-01), Kobayashi et al.
patent: 4894657 (1990-01-01), Hwang et al.
patent: 5027116 (1991-06-01), Armstrong et al.
patent: 5212486 (1993-05-01), Nagaraj
"CMOS Analog Circuit Design", P. E. Allen and D. R. Holberg, (1987) pp. 565-570.

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