Algorithm for testing a memory

Details Algorithm for testing a memory Algorithm for testing a memory

1994-07-27

1996-10-01

Beausoliel, Jr., Robert W.

Static information storage and retrieval

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365201, G06F 1100, G11C 700

Patent

active

055617654

ABSTRACT:
A method for generating test data for testing a memory having k data bits and n address bits, where n is less than or equal to 2 times k. For each address location for which test data is desired, the address bits for the location are combined to form the test data for the location. First, two mutually-exclusive groups of n minus k non-repeating bits of the address word are selected. Second, the two groups of address bits are combined using an exclusive-OR operation. Third, the results of the exclusive-OR operation are combined with any remaining bits of the address word to form the test data for the address location. For example, in one embodiment, the most significant n minus k bits of the least significant k bits of the address word are combined, via an exclusive-OR operation, with the most significant n minus k bits of the address word. The resulting data is then concatenated with the remaining bits of the address word.

REFERENCES:
patent: 4872168 (1989-10-01), Aadson et al.
patent: 5033048 (1991-07-01), Pierce et al.
patent: 5247524 (1993-09-01), Callon
patent: 5313475 (1994-05-01), Cromer et al.

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