Communications: electrical – Condition responsive indicating system – With particular system function
Reexamination Certificate
1999-09-23
2001-06-26
Pope, Daryl (Department: 2736)
Communications: electrical
Condition responsive indicating system
With particular system function
C340S507000, C340S526000, 37, 37
Reexamination Certificate
active
06252502
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to alarm detection apparatuses, and more particularly to an alarm detection apparatus which detects and/or cancels an alarm depending on an error rate of a data communication line.
In systems such as a Synchronous Optical Network (SONET) or a Synchronous Digital Hierarchy (SDH), a quality of a digital line is monitored by use of a B
2
byte (BIP: Bit Interleaved Parity-8) or a B
2
byte (BIP-8×N(in the case of the SONET)/BIP-N×24 (in the case of the SDH) of a frame format. The present invention is suited for application to such systems.
2. Description of the Related Art
FIG. 1
is a diagram showing a frame format of a SONET Synchronous Transport Signal-N (STS-N) for a case where N=192. At a transmitting end, a BIP operation result indicated by a hatched portion of an nth frame before scrambling is inserted into the B
2
byte of a (n+1)th frame before the scrambling. On the other hand, at a receiving end, a BIP operation result with respect to the nth frame after descrambling thereof and a B
2
byte of the (n+1)th frame after descrambling are compared, so as to detect a BIP error. According to STS-
192
, 1 B
2
byte is multiplexed 192 times, and BIP-8×
192
(8×192=1536 bits) BIP operations are carried out in total. Although not shown in
FIG. 1
, BIP operation and monitoring are similarly carried out with respect to the B
1
byte, although an operation range differs from that for the B
2
byte.
For the sake of convenience, the error rate will be described with respect to the BIP-
8
of the STS-
1
in order to simplify the description. The error rate for a case where only 1 bit within 1 frame is in error and no error exists in the other bits can be described by 1/(801×8)=1/6408≠1.5×10
−4
. Accordingly, it is possible to monitor whether or not the error rate is 1×10
−9
or greater, for example, by monitoring whether or not a BIP-
8
error of 1 bit exists in 1.5×10
5
frames or, a BIP-
8
error of 10 or more bits exist in 1.5×10
6
frames. Timewise, 1 frame period of the STS-N (STM-N) is 125 &mgr;sec, and thus, it requires at least approximately 19 sec in order to monitor the above error rate of 1×10
−9
. Actually, there are cases where a check is made to determine whether or not such a single bit error occurs 100 or more times so as to improve the monitoring accuracy. In such cases, the monitoring unit becomes 100 times the above period, that is, approximately 32 minutes.
FIG. 2
is a system block diagram showing a conventional alarm detector.
FIG. 2
shows a typical construction which is used in common for alarm detectors
10
1
through
10
10
which will be described later. In
FIG. 2
, an error counter (ERCT)
11
counts an error bit B
2
E of the BIP (B
2
byte), and a protection counter (PRCT)
12
counts a number of protection times of the alarm detection and/or cancellation. A frame counter (FRCT)
13
counts a frame pulse B
2
FP which has a period of 125 &mgr;sec and is generated in synchronism with the B
2
byte of the STS-N frame. A timing decoder (TDC
1
)
15
-
1
decodes a counter output Q of the frame counter
13
, and generates an alarm detection timing signal (for example,
1
T) which is used for alarm detection. A hysteresis counter (HYCT)
14
counts a pulse signal which is generated with a period of the alarm detection timing signal
1
T. A timing decoder (TDC
2
)
15
-
2
decides a counter output Q of the hysteresis counter
14
, and generates an alarm cancel detection timing signal (for example,
10
T which is 10 times the period) which is used for alarm cancel detection. Comparators (CM
1
, CM
2
)
17
-
1
and
17
-
2
, AND gate circuits (A
1
through A
5
)
18
-
1
through
18
-
2
, a selector (SL
1
)
16
, edge detection circuits (EG
1
, EG
2
and EG
4
through EG
6
)
19
-
1
,
19
-
2
and
19
-
4
through
19
-
6
for detecting rising and/or falling edges of input signals and generating edge pulse signals EP
1
, EP
2
and the like, a flip-flop (FF
1
)
1
for holding an alarm detection and/or cancel state, and OR gate circuits (ORI, OR
2
)
2
-
1
and
2
-
2
are connected as shown in FIG.
2
.
Although not shown in
FIG. 2
, a system clock signal CK
19
is input to a clock input terminal CK or the like of each of the counters
11
through
14
and the like. In addition, a system reset signal CL is input to a reset terminal R of each of the counters
11
through
14
and the flip-flop
1
.
Next, a description will be given of the operation of the alarm detector
101
. The alarm detector
10
1
is in an alarm detection mode when the flip-flop
1
is reset. In this case, the AND gate circuits
18
-
1
and
18
-
3
are closed, and the selector
16
selectively outputs the alarm detection timing signal
1
T. As a result, the error counter
11
counts the error bit signal B
2
E of the B
2
byte generated during an interval of the timing (gate) signal
1
T. In this state, the comparator
17
-
1
compares the counter output Q of the error counter
11
and a predetermined threshold value which is 980, for example. When the timing signal
1
T thereafter falls, the edge pulse signal EP
1
is generated in synchronism with this fall of the timing signal
1
T, and if the counter output Q of the error counter
11
is greater than or equal to 980 at this timing, the AND gate circuit
18
-
1
is opened and the protection counter
12
is incremented by +1. If the counter output Q of the error counter
11
is consecutively greater than or equal to 980 with respect to each detection period
1
T, the protection counter
12
is incremented by +1 each time. However, if the counter output Q of the error counter
12
becomes less than 980 at least once during the above time, the protection counter
12
is reset and the count is restarted from the beginning. In this state, the comparator
17
-
2
compares the counter output Q of the protection counter
12
and a predetermined threshold value which is 58, for example. Hence, if the counter output Q of the protection counter
12
is greater than or equal to 58 at the timing of each edge pulse signal EP
2
following the edge pulse signal EP
1
, the AND gate circuit
18
-
3
is opened and the flip-flop
1
is set to thereby output an alarm detection signal ALD
1
=1. In addition, when the flip-flop
1
is set, the protection counter
12
is reset, and the alarm detector
10
1
then assumes an alarm cancel detection mode.
In the alarm cancel detection mode, the AND gate circuits
18
-
2
,
18
-
4
and
18
-
5
are closed, and the selector
16
selectively outputs the alarm cancel detection timing signal
10
T. Hence, the error counter
11
counts the error bit signal B
2
E of the B
2
byte generated during an interval of the timing (gate) signal
10
T. In this state, the comparator
17
-
1
compares the counter output Q of the error counter
11
and the and a predetermined threshold value which is 980, for example. When the timing signal
10
T thereafter falls, the edge pulse signal EP
1
is generated in synchronism with this fall of the timing signal
10
T, and if the counter output Q of the error counter
11
is less than 980 at this timing, the AND gate circuit
18
-
2
is opened and the protection counter
12
is incremented by +1. If the counter output Q of the error counter
11
is consecutively less than 980 with respect to each detection period
10
T, the protection counter
12
is incremented by +1 each time. However, if the counter output Q of the error counter
12
becomes greater than or equal to 980 at least once during the above time, the protection counter
12
is reset and the count is restarted from the beginning. In this state, the comparator
17
-
2
compares the counter output Q of the protection counter
12
and a predetermined threshold value which is 58, for example. Hence, if the counter output Q of the protection counter
12
is greater than or equal to 58 at the timing of each edg
Ishiwatari Junichi
Kameda Masaru
Kobayashi Shigeyuki
Kubo Masaki
Nakayama Shuniti
Fujitsu Limited
Helfgott & Karas P.C.
Pope Daryl
LandOfFree
Alarm detection apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Alarm detection apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Alarm detection apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2459258