Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-11-05
2001-05-15
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S412000, C257S634000, C257S758000
Reexamination Certificate
active
06232647
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of electrically conductive traces in a semiconductor process. More specifically, the present invention relates to the formation an electrically insulating air gap between traces which implement borderless contacts.
2. Discussion of Related Art
FIG. 1
is a cross-sectional view of a semiconductor structure
100
which includes electrically conductive traces
101
and
102
formed over an insulating layer
103
and a semiconductor substrate
104
. A dielectric material
105
is formed over traces
101
and
102
, thereby isolating these traces. An air gap
106
is located in the dielectric material
105
, between traces
101
and
102
. The dielectric constant of the air gap
106
is significantly less than the dielectric constant of the dielectric material
105
. As a result, the air gap
106
reduces the capacitance between traces
101
and
102
. This reduced capacitance improves the speed of signal transmission on traces
101
and
102
.
FIG. 2A
is a top view of a semiconductor structure
200
which includes a borderless contact.
FIG. 2B
is a cross sectional view of semiconductor structure
200
along section line
2
B—
2
B of FIG.
2
A. Semiconductor structure
200
includes a first electrically conductive trace
201
formed over an insulating layer
202
and a semiconductor substrate
203
. A dielectric material
204
is formed over first trace
201
. A via
205
extends through dielectric material
204
to expose a portion of trace
201
. Via
205
need not be precisely aligned with trace
201
. Rather, an offset
206
may exist with respect to the first trace
201
and via
205
. The allowable offset
206
is determined by the accuracy of the processing parameters. A second electrically conductive trace
207
is deposited over the dielectric material
204
and into via
205
, such that the second trace
207
makes an electrical connection with the first trace
201
. In another conventional semiconductor structure, a conductive via plug is deposited in via
205
prior to forming the second trace
207
.
The interconnect structure illustrated in
FIG. 2
is referred to as a borderless contact because the first trace
201
does not include an enlarged area (i.e., a ‘border’) of conductive material where the via
205
is to be formed. That is, the width of the first trace
201
is substantially uniform along its length.
For purposes of comparison,
FIG. 3
shows a top view of a semiconductor structure
300
which was commonly used prior to the introduction of borderless contacts. Semiconductor structure
300
includes a first conductive trace
301
having a wide pattern
302
(i.e., a ‘border’) at the location where the via
303
is to be formed. A second conductive trace
304
extends into the via
303
to contact the first trace
301
. The wide pattern
302
provides a larger area for locating the via
303
. However, this wide pattern
302
undesirably increases the contacted pitch of the resulting interconnect structure. (The contacted pitch is defined as the minimum center to center spacing between adjacent traces.) Borderless contacts therefore advantageously improve the density of semiconductor structures.
FIG. 4A
is a top view of a conventional semiconductor structure
400
which includes both an air gap and a borderless contact.
FIG. 4B
is a cross sectional view of semiconductor structure
400
along section line
4
B—
4
B of FIG.
4
A. As illustrated in
FIG. 4B
, a pair of electrically conductive traces
401
and
402
are formed over an insulating layer
403
and a semiconductor substrate
404
. Traces
401
and
402
are separated by a first distance X
1
. A dielectric material
405
is formed over traces
401
and
402
. A via
406
extends through dielectric material
405
to expose conductive trace
401
. An electrically conductive via plug
407
is formed in via
406
. The via
406
has an offset X
2
with respect to trace
401
.
An air gap
408
having a constant width X
3
is centered between traces
401
and
402
. Air gap
408
is positioned a minimum distance X
4
from via
406
, thereby preventing via
406
from contacting air gap
408
. Via
406
must be separated from air gap
408
to prevent via plug
407
from inadvertently being deposited into air gap
408
. If via plug
407
were inadvertently deposited into air gap
408
, a relatively large capacitance would exist between traces
401
and
402
, thereby resulting in a loss of signal transmission speed on traces
401
and
402
. Consequently, it is desirable for distance X
4
to be sufficiently large to prevent the via
406
from contacting the air gap
408
. However, increasing the distance X
4
undesirably increases the contacted pitch between traces
401
and
402
. As a result, the density of the semiconductor structure
400
undesirably decreases.
It is also desirable to increase the width X
3
of air gap
408
, such that the capacitance between traces
401
and
402
is minimized. However, increasing the width of air gap
408
undesirably increases the layout area of the semiconductor structure
400
and/or increases the probability that via
406
will contact air gap
408
.
It is also desirable for the allowable offset X
2
of via
406
to be as large as possible to improve the density of the borderless contact. However, increasing the offset X
2
increases the probability that via
406
will contact air gap
408
.
It would therefore be desirable to have a semiconductor structure which combines borderless contact and air gap technologies in a manner which overcomes the previously described deficiencies of the prior art.
SUMMARY
Accordingly, the present invention provides a semiconductor structure having a first trace fabricated adjacent to a second trace over an insulating layer. A dielectric material is located over and between the first and second traces. A borderless contact extends through the dielectric material to contact the first trace. An air gap is located in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width at locations away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. In addition, the first portion of the air gap is offset toward the second trace.
The second portion of the air gap maximizes the average capacitance between the first and second traces, while the first portion of the air gap minimizes the contacted pitch of the first and second traces. Because the first air gap portion is relatively narrow and offset toward the second trace, additional area is advantageously provided for locating the borderless contact.
In an alternative embodiment of the invention, the first air gap portion is completely filled with dielectric material, thereby eliminating the first air gap portion. In this embodiment, the second air gap portion is still available to insulate the first and second traces along almost the entire length of the traces. This embodiment provides even more area for locating the borderless contact.
The present invention also includes methods for fabricating a semiconductor which includes both a borderless contact and an air gap. One such method includes the steps of (1) forming a first trace and a second trace adjacent to one another over an insulating layer, (2) locating a dielectric material over the first and second traces such that an air gap extends through the dielectric material between the first and second traces, the air gap having a first width along a first portion of the air gap and a second width along a second portion of the air gap, the second width being greater than the first width, and the first portion of the air gap being located closer to the second trace than the first trace, (3) forming a via t
Lee Shih-Ked
Lien Chuen-Der
Yen Chu-Tsao
Bever Hoffman & Harms LLP
Integrated Device Technology Inc.
Niebling John F.
Zarneke David A.
LandOfFree
Air gap with borderless contact does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Air gap with borderless contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Air gap with borderless contact will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2558138