Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2000-10-02
2002-09-24
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S221000, C438S459000, C438S692000
Reexamination Certificate
active
06455393
ABSTRACT:
FIELD OF THE INVENTION
This invention relates, in general, to integrated circuit structures and fabrication methods and, in particular, to isolation of circuit components using the etching of porous silicon areas followed by a dielectric backfill; including decoupling of circuit structure radio frequency transmission lines from a semiconductor substrate to minimize parasitics.
BACKGROUND OF THE INVENTION
Integrated circuits have been designed to ever-smaller geometries, and required to carry signals of ever-increasing frequencies. As integrated circuit components and signal lines are placed more closely together, and as the frequencies at which the components and signal lines operate are increased to radio frequencies (RF), the components and signal lines strongly couple electromagnetically to the substrate. This results in low power efficiency and restricts the maximum frequency at which the integrated circuit can function.
Previous methods have attempted to overcome the problem of coupling by increasing space between radiant components and receptive components, which results in larger die area and increased design costs. Other previous techniques have boosted the voltage levels of low voltage signals requiring a high degree of isolation; resulting in lower power efficiency and relatively high power emissions that may couple undesirably with other signals.
Previous designs. have used trenches to isolate components from a substrate; but such attempts typically fail to yield the 100 decibels (dB) of isolation necessary to integrate systems comprising mixed signal devices (such as base band, phase-locked-loop, or voltage controlled oscillators) or functionally distinct circuits requiring different power levels (such as transmitter or receiver) on the same substrate.
Even by changing the substrate, or isolating the component from the substrate, the degrees of isolation necessary to integrate many RF systems on a single chip have not been achieved. Thus, commercially viable isolation of RF components from the substrate is now needed.
SUMMARY OF THE INVENTION
Therefore, a method for fabricating an integrated circuit having active components, high frequency conductors and isolation regions on a substrate is now needed; providing enhanced design performance while overcoming the aforementioned limitations of conventional methods.
The present invention provides integrated circuit structures and fabrication methods, including techniques using the etching of porous silicon areas and dielectric backfill to provide isolation for circuit components. The present invention provides for isolation of circuit components, including decoupling of RF transmission lines on a circuit structure from a semiconductor substrate, to minimize parasitics. The present invention provides a method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate.
An embodiment of the present invention comprises patterning and etching at a portion of at least one of the isolation regions to expose a first area of the substrate; depositing a layer of silicon carbide (or other material resistant to a porous silicon formation process) over the substrate including the first area, patterning and etching the silicon carbide layer to expose a second area of substrate within the first area, forming a porous silicon region in at least the second area using HF (Hydrogen Fluoride), wherein the silicon carbide layer protects the active areas from the HF, forming at least one dielectric layer over the substrate, forming at least one patterned metallization layer over the dielectric layer, removing the porous silicon from the backside to form a void, and backfilling the void left,by the removal with a dielectric.
One embodiment of the present invention may form angled sidewalls having a slope between 30° and 60° degrees via the step of patterning and etching the isolation regions. This formation can comprise an isotropic plasma etch using CF
4
/O
2
, as well as an HF etch.
The present invention may comprise forming an oxide layer over the substrate patterned metallization comprising RF transmission lines; where the removal of porous silicon and backfilling with dielectric decouples RF transmission lines on the circuit structure from the semiconductor substrate to minimize parasitics.
In one embodiment of the present invention, the step of depositing a layer of silicon carbide is accomplished by using a silicon carbide layer with a thickness in the range of 500-5000 Å.
In another embodiment of the present invention, the fabrication of an RF integrated circuit having active components, high frequency conductors and isolation regions on a substrate, comprises the forming of isolation regions in a substrate; forming active components in said substrate; patterning at least one of the isolation regions to expose a first area of said substrate; etching away some of the field oxide; forming a patterned masking layer of silicon carbide over said substrate, preferably by Plasma Enhanced Chemical Vapor Deposition (PECVD); patterning and etching the silicon carbide layer to expose a second area of the substrate within the first area; anodizing the porous silicon region; exposing the porous silicon from the backside, e.g., by back grinding; removing the porous silicon from backside; and spin-coating on glass to fill voids left by the removal.
In some embodiments, especially those for high frequency applications, a low-dielectric constant material, such as porous silicon dioxide, e.g., as formed by an aerogel or HSQ process, is used as the dielectric, filling the voids left by the removal of the porous silicon.
A stabilizing material, such as a photoresist, can be used to level and strengthen the topside of the wafer, prior to the back-grinding step. The steps of back-grinding, removal of the porous silicon, and back-filling with dielectric may all be done in the same machine to avoid handling of the wafer while it is in a relatively fragile condition.
In one embodiment, there is a step of drying out porous silicon at 100-200° C. in vacuum for 6 to 24 hours, then heating in oven at 300-400° C. in oxygen for 1 hour; shifting from oxygen to nitrogen, to reduce the oxygen concentration in the porous silicon before depositing a capping layer.
In another embodiment, the anodization to form porous silicon is continued until the porous silicon extends entirely through the substrate and the need for back-grinding is eliminated.
The present invention may thus be utilized for isolation in general, not just to decouple conductors from the substrate to minimize RF parasitics. Areas in a substrate may be isolated from one another, even down to an individual transistor level, if desired.
REFERENCES:
patent: 5332469 (1994-07-01), Mastrangelo
Brady W. James
Chaudhuri Olik
Huynh Yennhu B.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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