Aggregate bandwidth through management using insertion of...

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

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C717S154000, C711S137000, C711S119000, C712S227000

Reexamination Certificate

active

10853304

ABSTRACT:
A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.

REFERENCES:
patent: 4991088 (1991-02-01), Kam
patent: 5551001 (1996-08-01), Cohen et al.
patent: 5692152 (1997-11-01), Cohen et al.
patent: 5704053 (1997-12-01), Santhanam
patent: 5797013 (1998-08-01), Mahadevan et al.
patent: 5854934 (1998-12-01), Hsu et al.
patent: 5953531 (1999-09-01), Megiddo et al.
patent: 6148439 (2000-11-01), Nishiyama
patent: 6249845 (2001-06-01), Nunez et al.
patent: 6301641 (2001-10-01), Verhoeven et al.
patent: 6374330 (2002-04-01), Arimilli et al.
patent: 6421826 (2002-07-01), Kosche et al.
patent: 6539541 (2003-03-01), Geva
patent: 6567976 (2003-05-01), Wolf
patent: 6571318 (2003-05-01), Sander et al.
patent: 2002/0007484 (2002-01-01), Tirumalai et al.
patent: 2002/0010913 (2002-01-01), Ronstrom
patent: 2003/0005419 (2003-01-01), Pieper et al.
patent: 2003/0088864 (2003-05-01), Tirumalai et al.
patent: 2004/0123081 (2004-06-01), Knies et al.
patent: 2004/0154019 (2004-08-01), Aamodt et al.
Barua, R. “Communication-Minimal Partitioning of Parallel Loops and Data Arrays for Cache-Coherent Distributed-Memory Multiprocessors”, Proceedings Languages and Compilers for Parallel Computing, 9thInternational Workshop, LCPC '96, p. 350-368 Aug. 1996.
Aschenbrenner, J. M. “Zeroing Memory Using Data Cache Line”, IBM TDB, v 40 n 2, p. 221-222, Feb. 1997.

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