Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
2001-03-15
2004-05-11
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S002000, C257S004000, C257S028000, C257S030000, C257S055000
Reexamination Certificate
active
06734455
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit fabrication and, more particularly, to fabrication of chalcogenide integrated circuit devices and chalcogenide integrated circuit structures.
BACKGROUND OF THE INVENTION
In the field of integrated circuit memory devices, there is a continuing trend toward memories that have store more information, consume less power, operate faster, take up less space, and cost less to make. While these are often competing interests, memory manufactures strive to make advances in these areas to remain competitive. Thus, the ability to manufacture small memory cells efficiently is crucial in maximizing the performance and cost-efficiency of a memory device.
Popular memories today include dynamic random access memories (DRAMs), static random access memories (SRAMs), read only memories (ROMs), and flash memories. Certain basic characteristics are shared by these memories. For example, these memories typically include one or more memory arrays, where each array has a plurality of memory cells arranged in rows and columns. Other than these basic characteristics, however, these memories possess many different attributes. By way of a general comparison, ROMs and flash memories do not exhibit true random access as do DRAMs and SRAMs. Also, DRAMs and SRAMS are volatile memories. DRAMS require constant power to retain and refresh the contents of the memory. SRAMs require constant power to retain the contents of the memory. ROMs, and flash memories are non-volatile memories. Furthermore, DRAMs typically require less area on a die than the other memories, but DRAMs generally do not exhibit the fastest access times. Thus, as can be appreciated due to the many trade-offs between these different memory configurations, the type of memory used greatly depends upon the requirements of the system in which it is used.
One reason for these differences may be understood by referring to the memory cells used by these various memories. Although the memory cells of these different memories store data in the form of an electrical charge, the memory cells take different forms. The form of a memory cell may dictate many of a memory's characteristics. For instance, the memory cell of a typical dynamic random access memory (DRAM) generally includes a memory element and an access device. The memory element is typically a small capacitor, which stores data as the presence or absence of an electrical charge on the capacitor. The access device, typically referred to as an access transistor, is electrically coupled to the small capacitor and controls the charging and discharging of the capacitor.
DRAMs possess many desirable features, such as large storage capacity, high storage density, and ease of manufacture. However, due to the type of memory cell used, DRAMs also require periodic refreshing, i.e., the capacitors need to be periodically recharged, to maintain the stored information. Although the memory cells of ROMs, and flash memories do not require refreshing, they suffer from disadvantages, such as lower storage densities, larger size, and greater cost to manufacture.
Instead of using memory cells that store information in the form of an electrical charge, memory cells may be manufactured of a material that is capable of storing information. Chalcogenides are a class of materials that may be used to store information in an integrated circuit memory. Chalcogenide material may be electrically stimulated to change states, from an amorphous state to increasingly crystalline states. In the amorphous state, chalcogenide material exhibits a high electrical resistivity. As chalcogenide material progresses into an increasingly crystalline state, its electrical resistivity generally decreases. Because chalcogenide material retains its programmed state even after removal of the electrical stimulus, chalcogenide-based memories are non-volatile. As an added benefit, chalcogenide elements may be repeatedly programmed into two or more states. Thus, chalcogenide-based memories may operate as traditional binary memories or as higher-based memories.
In chalcogenide-based memories, the memory cells are typically formed by disposing chalcogenide material between two electrodes. Examples of chalcogenide-based memories are discussed in U.S. Pat. No. 6,025,220 issued to Sandu; U.S. Pat. No. 6,087,689 issued to Reinberg; U.S. Pat. No. 6,117,720 issued to Harshfield; each assigned to Micron Technology, Inc. and each incorporated herein by reference. As discussed in these patents, U.S. Pat. No. 5,335,219 issued to Ovshinsky et al. provides an explanation of the function and operation of chalcogenide elements and their use in memory cells. U.S. Pat. No. 5,335,219 is also incorporated herein by reference.
A brief description of a conventional chalcogenide memory cell fabrication technique is now provided with reference to
FIGS. 1A-1D
. A bottom electrode
105
is formed on a substrate (not shown).
FIG. 1A
shows a chalcogenide, first material layer
107
formed on the bottom electrode
105
. A second material layer
109
is formed on the first layer
107
. The second layer
109
is then exposed to ultraviolet radiation, which drives the material of second layer
109
into the first layer
107
to create a doped, active chalcogenide material layer
110
(FIG.
1
B). A top electrode material is then sputtered on chalcogenide material layer
110
(FIG.
1
C). The top electrode material may be a noble metal such as silver. However, the top electrode
115
includes agglomerations or protrusions
120
on the surface thereof (FIG.
1
D).
FIG. 2
shows a 5 &mgr;m×5 &mgr;m area atomic force microscopy image of the protrusions
120
on the upper surface of top electrode
115
with the chalcogenide material layer
110
being GeSe doped with Ag and the top electrode
115
being Ag. The top electrode is 1000 Å thick. The protrusions
120
have an average height of about 550 Å and create a surface roughness rms of 140 Å. The surface of the electrode also has a terrace area height around the protrusions of 95 Å. It is also noted that the protrusions are visible even for very thin electrode thicknesses such as 100 Å.
In light of the foregoing, there is a need for fabrication of chalcogenide memory devices which reduce agglomeration of sputtered material on the chalcogenide.
SUMMARY OF THE INVENTION
The above mentioned problems with thin film fabrication techniques are addressed by the present invention and will be understood by reading and studying the following specification. The fabrication technique of the present invention includes forming a barrier layer on the layer to be diffused into the chalcogenide layer. Thus, prior to diffusing material into the chalcogenide layer the barrier layer is formed on a stacked layer to be diffused and the chalcogenide layer. In one embodiment according to the teachings of the present invention, the barrier layer is essentially transparent to the irradiation for driving the diffusing material into the chalcogenide layer. In another embodiment, the chalcogenide layer and the barrier layer include the same material.
In one embodiment according to the teachings of the present invention, a memory storage device is formed having a first electrode, a second electrode and a chalcogenide layer intermediate the first and second electrode. The second electrode has a smooth surface. In one embodiment, the smooth surface has an rms surface roughness of less than 140 Å, and, in another embodiment, the rms surface roughness is about 10.8 Å. Another embodiment includes the smooth surface having reduced height protrusions thereon.
Additional embodiments of the invention include methods, structures, deposition devices and systems for forming films on substrates, and machine readable media having fabrication instructions stored thereon as described herein.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part
Dickstein , Shapiro, Morin & Oshinsky, LLP
Eckert George
Fenty Jesse A.
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