AGC with non-linear gain for PLL circuits

Details AGC with non-linear gain for PLL circuits AGC with non-linear gain for PLL circuits

1992-05-29

1994-03-08

Shoop, Jr., William M.

Electricity: motor control systems

Closed loop speed control system for dc motor with commutator

Armature control by digital or combined analog and digital...

388911, 388912, H02P 5165

Patent

active

052934454

ABSTRACT:
A circuit automatically changes the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation. The circuit includes a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference. A counter counts clock pulses throughout the duration of the output signal, and a motor driving circuit drives the motor in response to the count reached by the counter. A source of clock pulses provides clock signals at first and second frequencies, the second frequency being lower than the first frequency, and a lock range sense circuit produces a sense signal output that indicates when the PLL is within a predetermined phase difference range. A circuit responsive to the sense signal output selectively applies the first frequency to clock the counter when the PLL is within the predetermined phase difference range, and to apply the second frequency to clock the counter when the PLL is operating outside of the predetermined phase difference range.

REFERENCES:
patent: 4104570 (1978-08-01), Hamby et al.
patent: 4301395 (1981-11-01), Furuhata et al.
patent: 4464620 (1984-08-01), Schwager et al.
patent: 4543516 (1985-09-01), Kobori et al.
patent: 4564794 (1986-01-01), Kilen et al.
patent: 4599545 (1986-07-01), Moriki et al.
patent: 4739237 (1988-04-01), Maruta
patent: 4816722 (1989-03-01), Shigemori
patent: 5087994 (1992-02-01), Fukushima
patent: 5093891 (1992-03-01), Komiyama et al.

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