Affine conversion apparatus using a raster generator to reduce c

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340747, 364521, 382 44, 382 46, G06K 932

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active

048398268

ABSTRACT:
An image processing apparatus including an affine conversion address generator, an image read memory, and an image write memory are connected via a control bus. The image read and write memories are connected via an image bus which operates independently of the control bus. Image data, which is designated by an affine conversion address output from the affine conversion address generator onto the control bus, is read out from the image read memory. The read image data is then transferred to the image write memory together with a busy signal indicating data transfer via the image bus. The image write memory stores the transferred image data in accordance with raster addresses sequentially generated therein.

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patent: 4636783 (1987-01-01), Omachi
patent: 4672680 (1987-06-01), Middleton
patent: 4680630 (1987-07-01), Field

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