Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-06-29
2003-07-01
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S077000, C257S314000, C257S321000, C257S407000, C257S412000, C257S741000, C438S503000, C438S507000, C438S509000
Reexamination Certificate
active
06586785
ABSTRACT:
BACKGROUND OF THE INVENTION
Driven by a strong demand for portable electronic devices, non-volatile memory represents an important and rapidly growing sector of today's semiconductor memory market. Polysilicon floating gate memory devices conventionally have held the largest market share of non-volatile memory devices. In today's rapidly emerging non-volatile memory device sector, non-volatile floating gate memory devices have been fabricated by embedding silicon nanoparticles within the gate oxide of metal-oxide semiconductor field effect transistors (MOSFETs). Nanoparticles are so named because they include particle diameters on the nanometer scale. It is believed that silicon nanoparticle floating gate memory devices outperform conventional floating gate memory devices with faster read and write times, higher reliability, and lower power dissipation. The memory operation of nanoparticle field effect transistors depends on charge storage, similar to conventional non-volatile memory devices. In a nanoparticle non-volatile memory device, however, charge is not stored on a continuous floating gate polysilicon layer as in the conventional technology, but instead on a layer of discrete, preferably crystalline silicon nanoparticles which may alternatively be referred to as nanocrystals or quantum dots.
In these nanoparticle floating gate memory devices, the nanoparticles that act as charge storage elements are located within the gate oxide of a MOSFET. Injecting charge into the nanoparticles by tunneling from the channel alters the threshold voltage of the transistor. A normal write/read/erase cycle includes information being written by injecting charge from the channel into the nanoparticles, reading by measuring the subthreshold current-voltage characteristics, and erasing by removing charge from the particles to the channel. A single electron stored on each nanoparticle in an array with a nanoparticle density of 3-10×10
11
/cm
2
results in a threshold voltage shift of 0.3-0.5 volts that is easily detected at room temperature. Generally speaking, as compared to conventional stacked-gate non-volatile memory devices, nanoparticle charge-storage offers several potential advantages, such as: (1) simple, low cost device fabrication since a dual-polysilicon process is not required; (2) superior retention characteristics resulting from Coulomb blockade and quantum confinement effects, enabling the use of thinner tunnel oxides and lower operating voltages; (3) improved anti-ppunchthrough performance due to the absence of drain-to-floating gate coupling thereby reducing drain induced punchthrough, allowing higher drain voltages during readout, shorter channel lengths and consequently a smaller cell area; and (4) excellent immunity to stress induced leakage current (SILC) and defects, due to the distributed nature of the charge storage in the nanocrystal layer. Even if a significant fraction of the individual nanocrystals that form the floating gate, are shorted to the channel/substrate, the non-volatile memory device remains functional because the non-shorted nanocrystals continue to store sufficient charge. The switching speed of devices made of nanocrystal ensembles, however, is potentially limited by a distribution in charge transit times, charging voltages, and threshold shifts resulting from various shortcomings of the nanoparticle layer, such as the nanoparticle size and size distribution, nanoparticle density, layer planarity and uniformity, and nanoparticle-to-nanoparticle interaction, i.e., lateral conduction.
Thus, there is a demonstrated need in the art for a layer of nanoparticles of uniform size distribution and density. Similarly, there is a demonstrated need for fabricating silicon or silicon-compatible nanocrystals with controlled size distributions and oxide thicknesses that can be deposited on a substrate in a uniform and co-planar manner. It is also desirable to fabricate the layer of nanocrystals using a process sequence that is simple, reliable, low cost, easily controlled, repeatable, and free of contamination. Previous attempts at producing a layer of nanocrystals suitable for use in a field-effect transistor or other non-volatile memory devices, include the shortcomings of uncontrolled particle sizes, non-uniformity of particle deposition, high contamination levels, low density of the particle material, non-uniform density of the particles within the nanoparticle layer, and unpredictable planarity of the nanoparticle layer. Such irregular and unpredictable nanocrystal layers result in poor-performing or non-functional devices.
In conclusion, in order to produce non-volatile memory devices with faster read and write times, higher reliability and lower power dissipation, it is desirable to provide a contamination-free monolayer of nanocrystals of uniform density and particle size for use in floating-gate non-volatile memory devices.
SUMMARY OF THE INVENTION
To address these and other needs and in view of its purposes, the present invention provides a stratum of discrete particles, each including a crystalline core surrounded by a continuous dielectric shell. The particles of the stratum include a tightly controlled range of particle sizes in the nanometer range. The cores of the particles include a density which approaches the bulk density of the material of which the cores are formed. A majority of the particle cores are single crystalline. Adjacent semiconductor particles of the stratum are electrically insulated from each other by means of their dielectric shells. The stratum may be used to form various semiconductor and microelectronic devices.
According to one aspect of the present invention, the stratum is used to form the floating gate of a transistor which additionally includes a tunnel oxide formed beneath the stratum and an upper gate oxide formed above the stratum. In one embodiment, the transistor may include a stratum of discrete silicon nanoparticles arranged in a monolayer and in which at least 90% of the nanoparticles include a diameter of less than 10 nanometers. Adjacent semiconductor particles of the stratum are electrically insulated from each other.
According to another aspect of the present invention, the stratum used to form the floating gate of a transistor includes nanoparticles having cores which include a density that approaches the bulk density of the material of which the cores are formed and in which a majority of the cores are single crystalline
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Flagan,
Atwater Harry A.
Bell, II Lloyd D.
Boer Elizabeth
Flagan Richard C.
Ostraat Michele L.
California Institute of Technology
Christie Parker & Hale LLP
Tran Mai-Huong
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