Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Patent
1994-05-16
1996-05-28
Sikes, William L.
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
257511, 257512, 257513, 257514, H01L 2701, H01L 2704
Patent
active
055213995
ABSTRACT:
A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.
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Chu Shao-Fu S.
Hsieh Chang-Ming
Hsu Louis L. C.
Kim Kyong-Min
Mei Shaw-Ning
Abraham Fetsum
International Business Machines - Corporation
Sikes William L.
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