Advanced receiver with sliding window block linear equalizer

Details Advanced receiver with sliding window block linear equalizer Advanced receiver with sliding window block linear equalizer

2005-09-29

2009-08-04

Payne, David C (Department: 2611)

Pulse or digital communications

Equalizers

C375S297000, C375S240020

Reexamination Certificate

active

07570689

ABSTRACT:
A receiver or an integrated circuit (IC) incorporated therein includes a fast Fourier transform (FFT)-based (or hybrid FFT-based) sliding window block level equalizer (BLE) for generating equalized samples. The BLE includes a noise power estimator, first and second channel estimators, an FFT-based chip level equalizer (CLEQ) and a channel monitor unit. The noise power estimator generates a noise power estimate based on two diverse sample data streams. The channel estimators generate respective channel estimates based on the sample data streams. The channel monitor unit generates a first channel monitor signal including truncated channel estimate vectors based on the channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors. The FFT-based CLEQ generates the equalized samples based on the noise power estimate, one-block samples of the first and second sample data streams, the channel estimates and the monitor signals.

REFERENCES:
patent: 5319677 (1994-06-01), Kim
patent: 6154487 (2000-11-01), Murai et al.
patent: 6370190 (2002-04-01), Young et al.
patent: 6775329 (2004-08-01), Alamouti et al.
patent: 7006840 (2006-02-01), Bultan et al.
patent: 7330505 (2008-02-01), Fitton et al.
patent: 2002/0014983 (2002-02-01), Honkanen et al.
patent: 2003/0076908 (2003-04-01), Huang et al.
patent: 2004/0101072 (2004-05-01), Fitton et al.
patent: 2004/0248602 (2004-12-01), Demir et al.
patent: 2005/0025267 (2005-02-01), Reznik et al.
patent: 2006/0056496 (2006-03-01), Smee et al.
patent: 2006/0109897 (2006-05-01), Guo et al.
patent: 2006/0159201 (2006-07-01), Blasco Claret et al.
patent: 2008/0260013 (2008-10-01), Heikkila
Guo et al., “Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink”, Conference Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers, vol. 2, Nov. 2003, pp. 2171-2175.
3rdGeneration Partnership Project, “Technical Specification Group Radio Access Network; Physical Channels and Mapping of Transport Channels onto Physical Channels (FDD) (Release 5)”, 3GPP TS 25.211 V5.5.0, Sep. 2003.
Guo et al., “Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink”, Conference Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers, vol. 2, Nov. 2003, pp. 2171-2175.
3rdGeneration Partnership Project, “Technical Specification Group Radio Access Network; Physical Channels and Mapping of Transport Channels onto Physical Channels (FDD) (Release 5)”, 3GPP TS 25.211 V5.5.0, Sep. 2003.

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