Advanced programmable interrupt controller

Details Advanced programmable interrupt controller Advanced programmable interrupt controller

1996-08-02

1998-04-28

Auve, Glenn A.

395742, G06F 946

Patent

active

057457727

ABSTRACT:
A computer system having an advanced programmable interrupt controller (APIC) is described in which an I/O APIC module is included in core logic circuitry coupled between a processor bus and a system bus. An interrupt controller is included in bridge circuitry coupled between the system bus and an expansion bus. System and expansion bus devices requiring service output interrupt request signals (IRQs) which are received by the interrupt controller. The interrupt controller then outputs an interrupt signal which is received by the I/O APIC module. The I/O APIC module initiates a system bus acknowledge cycle to receive an interrupt vector from the interrupt controller. The I/O APIC module converts the interrupt vector into a system-appropriate APIC protocol and transmits the vector on an APIC bus to local APIC modules integrated within processors of the computer system. In one embodiment, the I/O APIC module receives the system bus device IRQs directly, and the system bus acknowledge cycle is required only to obtain the expansion bus device interrupt vectors.

REFERENCES:
patent: 5619705 (1997-04-01), Karnik et al.
patent: 5619706 (1997-04-01), Young
Intel Corporation, "MultiProcessor Specification, Version 1.4" Mt. Prospect, Illinois, Jul. 1995.
Intel Corporation, "82378ZB System I/O (SIO) and 82379AB System I/O APIC (SIO.A)," Mt. Prospect, Illinois, Mar. 1996.
Anderson, D.; Shanley, T., "Chapter 15: The APIC," pp. 317-372, Pentium Processor System Architecture, Second Edition, Massachusetts, Oct. 1995.

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