Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-03-04
1998-05-05
Le, Vu A.
Static information storage and retrieval
Floating gate
Particular biasing
36518505, 36518511, G11C 700
Patent
active
057485356
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to flash EEPROM memory technology, and more particularly to an improved flash EEPROM memory architecture for automatic program verify and for page programming.
2. Description of Related Art
Flash EEPROMs are a growing class of non-volatile storage integrated circuits. The memory cells in a flash EEPROM are formed using so-called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate of the transistor by a second layer of insulating material.
The floating gate may be charged through a Fowler-Nordheim tunneling mechanism by establishing a large positive voltage between the gate and source or drain. This causes electrons to be injected into the floating gate through the thin insulator. Alternatively, an avalanche injection mechanism, known as hot electron injection, may be used by applying potentials to induce high energy electrons in the channel of the cell which are injected across the insulator to the floating gate. When the floating gate is charged, the threshold voltage for causing the memory cell to conduct is increased above the voltage applied to the word line during a read operation. Thus, when a charged cell is addressed during a read operation, the cell does not conduct. The non-conducting state of the cell can be interpreted as a binary 1 or 0 depending on the polarity of the sensing circuitry.
The floating gate is discharged to establish the opposite memory state. This function is typically carried out by an F-N tunneling mechanism between the floating gate and the source or the drain of the transistor, or between the floating gate and the substrate. For instance, the floating gate may be discharged through the drain by establishing a large positive voltage from the drain to the gate, while the source is left at a floating potential.
The high voltages used to charge and discharge the floating gate place significant design restrictions on flash memory devices, particularly as the cell dimensions and process specifications are reduced in size.
Furthermore, the act of charging and discharging the floating gate, particularly when using the F-N tunneling mechanism, is a relatively slow process that can restrict the application of flash memory devices in certain speed sensitive applications.
Another process which slows down flash memory devices is program verify. After applying a program sequence, successful programming must be verified, and if a failure is detected, then the programming is retried. Program retries are typically executed word by word or byte by byte. Thus, bits successfully programmed in a byte with one failed bit are subjected to the program cycle repeatedly. This can result in over programming and failure of the cell. For one approach to this issue, see U.S. patent application Ser. No. 5,163,021 by Mehrotra, et al., et seq. at col. 19, line 10 et seq. and FIGS. 14-17.
Therefore, it is desirable to provide a flash EEPROM cell architecture, and a method of programming the same which overcome speed penalties and over-programming failures of the prior art.
SUMMARY OF THE INVENTION
The present invention provides novel flash EEPROM cell and array designs, and methods for programming the same which result in improved speed. The novel flash EEPROM array design is based on "page mode" programming, which operates by writing a row of data which constitutes a page, including, for example, as many as 1024 flash EEPROM cells in parallel. Thus, according to one aspect of the present invention, a flash EEPROM transistor array is provided. The memory array has a plurality of flash EEPROM cells for storing data. Supply circuits apply voltages to the plurality of flash EEPROM cells to read and program the plurality of flash EEPROM cells in the m
REFERENCES:
patent: 4054864 (1977-10-01), Audaire et al.
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 4890259 (1989-12-01), Simko
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5218569 (1993-06-01), Banks
patent: 5245570 (1993-09-01), Fazio et al.
patent: 5283758 (1994-02-01), Nakayama et al.
patent: 5294819 (1994-03-01), Simko
patent: 5297081 (1994-03-01), Challa
patent: 5323351 (1994-06-01), Challa
patent: 5357463 (1994-10-01), Kinney
patent: 5363330 (1994-11-01), Kobayashi et al.
patent: 5369609 (1994-11-01), Wang et al.
patent: 5379256 (1995-01-01), Tanaka et al.
patent: 5414658 (1995-05-01), Challa
patent: 5418743 (1995-05-01), Tomioka et al.
patent: 5422845 (1995-06-01), Ong
patent: 5450363 (1995-09-01), Christopherson et al.
patent: 5615149 (1997-03-01), Kobayashi et al.
patent: 5625590 (1997-04-01), Choi et al.
patent: 5638326 (1997-06-01), Hollmer et al.
patent: 5646886 (1997-07-01), Brahmbhatt
Jung, T. et al., "A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications", 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 1996, pp. 32-33.
Bauer, M. et al., "A Multilevel-Cell 32Mb Flash Memory", 1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 1995, pp. 132-133.
Mills, D. et al., "A 3.3V 50MHz Synchronous 16Mb Flash Memory", Digest of Techical Papers, 1995 IEEE International Solid-State Circuits Conference, Session 7, Feb. 16, 1995, pp. 119-131.
Suh, K. et al., "A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme", 1995 IEEE International Solid-State Circuits Conference, Digest of Tech. Papers, Feb. 1995, pp. 128-129.
Tanaka, et al., "High-Speed Programming and Program-Verify Methods Suitable for Low-Voltage Flash Memories," 1994 Symposium on VLSI Circuits Digest of Technical Papers, 1994 IEEE, pp. 61-62.
Hung Chun-Hsiung
Lin Tien-Ler
Liou Kong-Mou
Soejima Kota
Takahashi Jun
Haynes Mark A.
Le Vu A.
Macronix International Co. Ltd.
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