Fishing – trapping – and vermin destroying
Patent
1994-06-15
1995-02-28
Fourson, George
Fishing, trapping, and vermin destroying
H01L 2176
Patent
active
053936949
ABSTRACT:
A process useful for isolating active areas of semiconductor devices, comprising the steps of: forming pad oxide, polysilicon, and nitride layers superjacent a substrate; patterning and etching the layers and the substrate, thereby forming a recess in the substrate; forming a nitride spacer within the recess, then growing a field oxide region therein; removing the layers thereby causing an indentation to form within the periphery of the field oxide region; disposing polysilicon within the indentation; etching the polysilicon to a level even with the field oxide region; and oxidizing the polysilicon.
REFERENCES:
patent: 4541167 (1985-09-01), Havemann
Toshiyuki Nishihara et al., "A 0.5um Isolation Technology Using Advanced Poly Silicon Pad LOCOS (APPL)", IEEE, 1988, pp. 100-103.
H. S. Yang et al., "Poly void Formation in Poly Buffer LOCOS Process", Extended Abstracts of the Spring Elecrochemical Society meeting, 1992, p. 442.
J. M. Sung, "The Impact of Poly-Removal Techniques on Thin Thermal Oxide Property in Poly-Buffer LOCOS Technology", IEEE Transactions on Electron Devices, Aug. 1991, pp. 1970-1973.
Stanley Wolf, "A Review of IC Isolation Technologies--Part 6", Solid State Technology, Dec. 1992, pp. 39-41.
R. L. Guldi, "Characterization of Poly-Buffered LOCOS in Manufacturing Environment", J. Electrochem. Soc., Dec. 1989, pp. 3815-3820.
Tin-hwang Lin, "Twin-White-Ribbon Effect and Pit Formation Mechanism in PBLOCOS", J. Electrochem. Soc., Jul. 1991, pp. 2145-2149.
M. Ghezzo, "LOPOS: Advanced Device Isolation for a 0.8um CMOS/BULK Process Technology", Journal of The Electrochemical Society, Jul. 1989, pp. 1992-1996.
N. Shimizu et al., "A Poly-Buffer Recessed LOCOS Process for 256Mbit DRAM Cells", IEEE, IEDM 92-279, 1992, pp. 10.6.1-10.6.4.
Fourson George
Micron Semiconductor Inc.
Pappas Lia M.
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