Boots – shoes – and leggings
Patent
1992-05-22
1996-12-31
Bowler, Alyssa H.
Boots, shoes, and leggings
364DIG1, 364DIG2, G06F 1300
Patent
active
055903452
ABSTRACT:
A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.
REFERENCES:
patent: 4245302 (1981-01-01), Amdahl
patent: 4873626 (1989-10-01), Gifford
patent: 4891787 (1990-01-01), Gifford
patent: 4925311 (1990-05-01), Neches et al.
patent: 5072371 (1991-12-01), Benner et al.
patent: 5129077 (1992-07-01), Hillis
patent: 5165023 (1992-11-01), Gifford
patent: 5181017 (1993-01-01), Frey, Jr. et al.
patent: 5212777 (1993-05-01), Gove et al.
patent: 5418970 (1995-05-01), Gifford
C. K. Baru and S. Y. W. Su, "The Architecture of SM3: A Dynamically Partitionable Multicomputer System", IEEE Transactions on Computers, vol. C-35, No. 9, pp. 790-802, Sep. 1986.
S. P. Booth et al., "An Evaluation of the Meiko Computing Surface for HEP Fortran Farming*", Computer Physics Communications 57, pp. 486-491, 1989.
S. P. Booth et al., "Large Scale Applications of Transputers in HEP: The Edinburgh Concurrent Supercomputer Project", Computer Physics Communications 57, pp. 101-107, 1989.
P. Christy, "Software to Support Massively Parallel Computing on the MasPar MP-1", 1990 IEEE, pp. 29-33.
S. R. Colley, "Parallel Solutions to Parallel Problems", Research & Development, pp. 42-45, Nov. 21, 1989.
E. DeBenedictis and J. M. del Rosario, "nCUBE Parallel I/O Software", IPCCC '92, 1992 IEEE, pp. 0117-0124.
T. H. Dunigan, "Hypercube Clock Synchronization", Concurrency: Practice and Experience, vol. 4(3), pp. 257-268, May, 1992.
T. H. Dunigan, "Performance of the Intel iPSC/860 and Ncube 6400 hypercubes *", Parallel Computing 17, pp. 1285-1302, 1991.
D. D. Gajski and J. K. Peir, "Essential Issues in Multiprocessor Systems", 1985 IEEE, pp. 9-27, Jun. 1985.
A. Holman, "The Meiko Computing Surface: A Parallel & Scalable Open Systems Platform for Oracle", A Study of a Parallel Database Machine and its Performance--The NCR/Teradata DBC/1012, pp. 96-114.
J. R. Nickolls, "The Design of the MasPar MP-1: A Cost Effective Massively Parallel Computer", 1990 IEEE, pp. 25-28.
J. F. Prins and J. A. Smith, "Parallel Sorting of Large Arrays on the MasPar MP-1*", The 3rd Symposium on the Frontiers of Massively Parallel Computation, pp. 59-64, Oct., 1990.
J. B. Rosenberg and J. D. Becher, "Mapping Massive SIMD Parallelism onto Vector Architectures for Simulation", Software-Practice and Experience, vol. 19(8), pp. 739-756, Aug., 1989.
J. C. Tilton, "Porting an Iterative Parallel Region Growing Algorithm from the MPP to the MasPar MP-1", The 3rd Symposium on the Frontiers of Massively Parallel Computation, pp. 170-173, Oct., 1990.
"Sequent Computer Systems Balance and Symmetry Series", Faulkner Technical Reports, Inc. pp. 1-6, Jan., 1988.
"Symmetry 2000/400 and 2000/700 with the DYNIX/ptx Operating System", Sequent Computer Systems Inc.
"Symmetry 2000 Systems--Foundation for Information Advantage", Sequent Computer Systems Inc.
"Our Customers Have Something That Gives Them an Unfair Advantage", The nCUBE Parallel Software Environment, nCUBE Corporation.
Y. M. Leung, "Parallel Technology Mapping With Identification of Cells for Dynamic Cell Generation", Dissertation, Syracuse University, May 1992.
"The Connection Machine CM-5 Technical Summary", Thinking Machines Corporation, Oct. 1991.
Fineberg et al., "Experimental Analysis of a Mixed-Mode Parallel Architecture Using Bitonic Sequence Sorting", Journal of Parallel and Distributed Computing, Mar. 1991, pp. 239-251.
Bridges, "The GPA Machine: A Generally Partitionable MSIMD Architecture", The 3rd Symposium on the Frontiers of Massively Parallel Computation, Oct. 1990, pp. 196-203.
Abreu et al., "The APx Accelerator", The 2nd Symposium on the Frontiers of Massively Parallel Computation, Oct. 1988, pp. 413-417.
Nicole, "Esprit Project 1085 Reconfigurable Transputer Processor Architecture", CONPAR 88 Additional Papers, Sep. 1988, pp. 12-39.
Barker Thomas N.
Collins Clive A.
Dapp Michael C.
Dieffenderfer James W.
Grice Donald G.
Augspurger Lynn L.
Bowler Alyssa H.
Darbe Valerie
International Business Machines - Corporation
Riddles Andrew M.
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