Boots – shoes – and leggings
Patent
1996-06-28
1998-11-03
Teska, Kevin J.
Boots, shoes, and leggings
364489, G06F 1750
Patent
active
058318631
ABSTRACT:
A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties.
REFERENCES:
patent: 3603771 (1971-09-01), Isett
patent: 3617714 (1971-11-01), Kernighan
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4342090 (1982-07-01), Caccoma et al.
patent: 4484292 (1984-11-01), Hong et al.
patent: 4495559 (1985-01-01), Gelatt, Jr. et al.
patent: 4554625 (1985-11-01), Otten
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4612618 (1986-09-01), Pryor et al.
patent: 4615011 (1986-09-01), Linsker
patent: 4621339 (1986-11-01), Wagner et al.
patent: 4630219 (1986-12-01), Digiacomo et al.
patent: 4656580 (1987-04-01), Hitchcock, Sr. et al.
patent: 4675829 (1987-06-01), Clemenson
patent: 4686629 (1987-08-01), Noto et al.
patent: 4688072 (1987-08-01), Heath et al.
patent: 4697242 (1987-09-01), Holland et al.
patent: 4754408 (1988-06-01), Carpenter et al.
patent: 4763288 (1988-08-01), Deering et al.
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 4829446 (1989-05-01), Draney
patent: 4831725 (1989-05-01), Dunham, et al.
patent: 4850027 (1989-07-01), Kimmel
patent: 4872125 (1989-10-01), Catlin
patent: 4908772 (1990-03-01), Chi
patent: 4910680 (1990-03-01), Hiwatashi
patent: 4918614 (1990-04-01), Modarres et al.
patent: 4961152 (1990-10-01), Davis
patent: 4965739 (1990-10-01), Ng
patent: 5051895 (1991-09-01), Rogers
patent: 5051938 (1991-09-01), Hyduke
patent: 5062054 (1991-10-01), Kawakami et al.
patent: 5119313 (1992-06-01), Shaw et al.
patent: 5124927 (1992-06-01), Hopewell et al.
patent: 5136686 (1992-08-01), Koza
patent: 5140402 (1992-08-01), Murakata
patent: 5140526 (1992-08-01), Mc Dermith et al.
patent: 5140530 (1992-08-01), Guha et al.
patent: 5144563 (1992-09-01), Date et al.
patent: 5157778 (1992-10-01), Bischoff et al.
patent: 5159682 (1992-10-01), Toyonaga et al.
patent: 5187668 (1993-02-01), Okude et al.
patent: 5191542 (1993-03-01), Murofushi
patent: 5200908 (1993-04-01), Date et al.
patent: 5202840 (1993-04-01), Wong
patent: 5208759 (1993-05-01), Wong
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5222029 (1993-06-01), Hooper et al.
patent: 5222031 (1993-06-01), Kaida
patent: 5224056 (1993-06-01), Chene et al.
patent: 5224057 (1993-06-01), Igarashi et al.
patent: 5225991 (1993-07-01), Dougherty
patent: 5231590 (1993-07-01), Kumar et al.
patent: 5239465 (1993-08-01), Hattori et al.
patent: 5245550 (1993-09-01), Miki et al.
patent: 5249259 (1993-09-01), Harvey
patent: 5251147 (1993-10-01), Finnerty
patent: 5255345 (1993-10-01), Shaefer
patent: 5267176 (1993-11-01), Antreich et al.
patent: 5267177 (1993-11-01), Sato et al.
patent: 5303161 (1994-04-01), Burns et al.
patent: 5309371 (1994-05-01), Shikata et al.
patent: 5341308 (1994-08-01), Mendel
patent: 5349536 (1994-09-01), Ashtaputre et al.
patent: 5363313 (1994-11-01), Lee
patent: 5392222 (1995-02-01), Noble
patent: 5398195 (1995-03-01), Kim
patent: 5404313 (1995-04-01), Shiohara et al.
patent: 5404561 (1995-04-01), Castelaz
patent: 5465218 (1995-11-01), Handa
patent: 5495419 (1996-02-01), Rostoker et al.
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5659717 (1997-08-01), Tse et al.
Algorithms For VLSI Physical Design Automation, N. Sherwani, Kluwer Academic Publishers, 1993, no page #.
Timber Wolf 3.2:A New Standard Cell Placement and Global Routing Package, C. Sechen and A. Sangiovanni-Vincentelli; IEEE 23rd Design Automaton Conf., 1986, Paper 26.1, no pg #.
A Genetic Approach to Standard Cell Placement Using Metagenetic Parameter Optimization, K. Shahookar and P. Mazumder; IEEE Transactions on Computer-Aided Design, vol. 9, No. 5, May 1990, no page #s.
Wolverines: Standard Cell Placement on a Network of Workstations, S. Mohan and P. Mazumder; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 9, Sep. 1993, no page #s.
The Stanford Dash Multiprocessor, D. Lenoski et al.; Computer, Mar. 1992, no page #.
Genetic Programming, J. Koza; MIT Press, Cambridge, MA. 1993, pp. 94-101 and 173.
The S3.MP Interconnect System & TIC Chip, A. Nowatzyk and M. Parkin; Proceedings of IEEE Computer Society Hot Interconnect Symposium, Stanford Univ., 1993, no page #.
Gordian: VLSI Placement by Quadratic Programming and Slicing Optimization, J. Kleinhans, G. Sigl, F. Johannes, and K. Antreich; IEEE Transactions on Computer-Aided Design, vol. 10, No. 3, Mar. 1991, no page #.
A Loosely Coupled Parallel Algorithm for Standard Cell Placement, W. Sun and C. Sechen; ACM, 1994, pp. 137-144.
An Improved Simulated Annealing Algorithm for Row-Based Placement, C. Sechen and K. Lee; IEEE Int'l . Conf. on Computer-Aided Design, Nov. 1987, pp. 478-481.
A Linear-Time Heuristic for Improving Network Partitions, C.M. Fiduccia and R.M. Mattheyses; IEEE 1982, 19th Design Automation Conferencee, Paper 13.1, pp. 175-181.
A Block Placement Procedure Using a Force Model, H. Onodera and K. Tamaru; Electronics and Communications in Japan, Part 3, vol. 72, No. 11, 1989, pp. 87-96.
Champ: Chip Floor Plan for Hierarchical VLSI Layout Design, K. Ueda, H. Kitazawa and I. Karada; IEEE Transactions on Computer-Aided Design, vol. CAD-4, No. 1, Jan. 1985, no page #.
A Forced Directed Component Placement Procedure for Printed Circuit Boards, N, Quinn, Jr., and M. Breuer; IEEE Transactions on Circuits and Systems, vol. CAS-26, No. 6, Jun. 1979, no page #.
Simultaneous Pin Assignment and Global Wiring for Custom VLSI Design, L.Y. Wang, Y.T. Lai, and B.D. Liu, IEEE, no date, no page #.
Pin Assignment with Global Routing for General Cell Designs, Jingsheng (Jason) Cong, IEEE Transaction on Computer-Aided Design, vol. 10, No. 11, Nov. 1991, no page #.
Floorplanning with Pin Assignment, Massoud Pedram, Malgorzata Marek-Sadowska, Ernest K. Kuh, 1990 IEEE, no page #.
A New Approach to the Pin Assignment Problem, Xianjin Yao, Massaki Yamada, C.L. Lis, 25th ACM/IEEE Design Automation Conference, 1988, Paper 37.3, no page #.
Placement of Standard Cells Using Simulated Annealing on the Connection Machine, Andrea Casotto, Alberto Sangiovanni-Vincentelli, 1987 IEEE, no page #.
Parallel Standard Cell Placement Algorithms with Quality Equivalent to Simulated Annealing, Jonathan S. Rose, W. Martin Snelgrove, Zvonko G. Vranesic, IEEE Transactions on Computer-Aided Design, vol. 7, No. 3, Mar. 1988, no page #.
Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube, Mark Jones, Prithviraj Baner Jee, 24th ACM/IEEE Design Automation Conference, p. 42.3, no date, no page #.
A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells, Andrea Casotto, Fabio Romeo and Alberto Sangiovanni-Vincentelli, no page #, no date.
Properplace: A Portable Parallel Algorithm for Standard Cell Placement, Sungho Kim, John A. Chandy, Steven Parkes, Balkrishna Ramkumar, Prithviraj Banerjee, 1994 IEEE, no page #.
A Cell-Replicating Approach to Mincut-Based Circuit Partitioning, Chuck Kring and A. Richard Newton, 1991 IEEE, no page #.
An Improved Simulated Annealing Algorithm for Row-Based Placement, Carl Sechen and Kai-Win Lee, 1987 IEEE, no page #.
A Loosely Coupled Parallel Algorithm for Standard Cell Placement; Wern-Jieh Sun and Carl Sechen, 1994, no page #.
Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout, W. Dai, E. Kuh, 1987 IEEE, no page #.
A New Clustering Approach and its Application to BBL Placement, M.Y. Yu, X.L. Hong, Y.E. Lien, Z.Z. Ma, J.G. Bo, W.J. Zhuang, 1990 IEEE, no page #.
Genetic Placement, J. P. Cohoon, W. D. Paris, 1986 IEEE, no page #.
Champ: Chip Floor Plan for Hierarchical VLSI Layo
Andreev Alexander E.
Koford James S.
Scepanovic Ranko
Garbowski Leigh Marie
LSI Logic Corporation
Teska Kevin J.
LandOfFree
Advanced modular cell placement system with wire length driven a does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Advanced modular cell placement system with wire length driven a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Advanced modular cell placement system with wire length driven a will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-697035