Boots – shoes – and leggings
Patent
1996-06-28
1999-06-22
Teska, Kevin J.
Boots, shoes, and leggings
364489, 364490, G06F 1750
Patent
active
059148888
ABSTRACT:
A computer implemented method for optimizing cell placement for integrated circuit design is provided herein. The method comprises the steps of segmenting an integrated circuit surface abstraction into a plurality of regions; assigning a plurality of cells to one of the regions; creating a list of said plurality of cells in order of decreasing cell height; reassigning said cells in order of the list such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region; and thereafter assigning the remaining cells outside of the region.
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Simultaneous Pin Assignment and Glo
Andreev Alexander E.
Koford James S.
Scepanovic Ranko
Kik Phallaka
LSI Logic Corporation
Teska Kevin J.
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