Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Lateral bipolar transistor structure
Reexamination Certificate
1999-08-10
2002-12-31
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Lateral bipolar transistor structure
C257S557000, C257S347000, C438S316000, C438S325000
Reexamination Certificate
active
06501152
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of forming bipolar transistors and more specifically to a method of forming a lateral bipolar transistor using a BiCMOS process.
BACKGROUND OF THE INVENTION
Lateral PNP bipolar transistors (LPNPs) are desired for many mixed signal integrated circuit (IC) designs. Mixed signal ICs combine both digital and analog circuitry and thus typically comprise CMOS transistors as well as NPN bipolar transistors, high performance capacitors, LPNPs and sometimes resistors. LPNPs may be used in applications such as current mirrors, active loads, and complementary bipolar logic. An example of a critical circuit application for a LPNP is the filter null circuit where the LPNP current mirror has been shown to out-perform the best design using a PMOS based current mirror. The LPNP has higher dynamic range, higher transconductance, lower parasitic capacitance, low operating voltage, higher bandwidth (3×PMOS), less gain variation due to output voltage, and lower DC offset voltage. As a result, LPNPs are very desirable for hard disk drive (HDD) applications.
A typical LPNP design for a mixed signal IC is shown in FIG.
1
. Because the LPNP is formed using a BiCMOS process, the formation of the LPNP is designed to use as many of the steps for forming the CMOS transistors as possible. A N+ buried layer
14
is formed in a substrate
12
and functions as the low resistance base of the LPNP
10
. N-well
16
is the base of the LPNP
10
. The emitter
18
and collector
20
are formed in N-well
16
using a standard p+ source/drain (S/D) and drain extension implants. The polysilicon (poly) gate electrode
22
is tied to the emitter region
18
. LPNP
10
is essentially an inherent PNP of a PMOS transistor optimized for PNP performance. Isolation regions
24
isolate LPNP
10
from other devices (not shown) and from the base contact
26
.
There are two dominant currents in LPNP
10
. The first is the base or parasitic current. The base current is the electrons and holes injected vertically between the n-well
16
and emitter
18
junction area. The second dominant current is the collector or active current. The collector current is the holes diffused laterally through the “channel” region
28
of the base n-well
16
between the emitter
18
and collector
20
.
LPNPs achieve gain from the active current. However, the gain is reduced by the parasitic current. The gain (beta) of the LPNP is proportional to the ratio of the periphery to the area of the emitter S/D diffusion or the ratio of the active to parasitic base-emitter junction. As a result, Beta is proportional to 1/(length of the polysilicon gate):1/(base width). Accordingly, the gain (beta) can be increased by decreasing the poly gate length. However, since the collector and emitter profiles are constant (i.e., fixed by the CMOS design parameters), the early voltage is proportional to the length of the polysilicon gate
22
. (The early voltage is proportional to the sum of the active base doping.) Thus. increasing the gate length improves the early voltage. As a result, the beta*early voltage product, a measure of the performance of the LPNP, is relatively constant for a given CMOS technology regardless of base width.
The LPNP typically uses a layout having a circular collector to improve the periphery to area ratio of the emitter.
FIG. 2
shows a cross-section of a circular collector LPNP
10
and
FIG. 3
is a top view of the same device. A gate length of 0.6 microns results in a beta (gain) of 16 and an early voltage of 12, for a total product of 192. If the gate length is increased to 0.8 microns, the beta is 9 and the early voltage is 20 for a product of 180. The different is relatively insubstantial. For HDD applications, both a beta and early voltage of 20 is desired. Accordingly, improvements in the gain and/or early voltage are needed without substantial increases in process cost.
SUMMARY OF THE INVENTION
A method of forming a LPNP transistor is disclosed herein. The standard CMOS drain extension implants are blocked from the emitter region, but not from the collector region of the LPNP. Accordingly, the emitter region has a more abrupt junction for high emitter injection efficiency while the collector region has a lightly doped region for reduced base depletion.
An advantage of the invention is providing a LPNP having improved beta (gain)*early voltage product.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
REFERENCES:
patent: 5717241 (1998-02-01), Malhi et al.
patent: 5965923 (1999-10-01), Prall et al.
patent: 6157065 (2000-12-01), Huang et al.
patent: 6281530 (2001-08-01), Johnson
Brady III W. James
Garner Jacqueline J.
Kang Donghee
Loke Steven
Telecky , Jr. Frederick J.
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