Advanced high-k gate stack patterning and structure...

Details Advanced high-k gate stack patterning and structure... Advanced high-k gate stack patterning and structure...

2007-03-13

2010-10-26

Smith, Bradley K (Department: 2894)

Semiconductor device manufacturing: process

Chemical etching

Having liquid and vapor etching steps

C438S689000, C257SE21214, C257SE29226

Reexamination Certificate

active

07820552

ABSTRACT:
An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010atoms/cm2, preferably less than about 109atoms/cm2.

REFERENCES:
patent: 6893927 (2005-05-01), Shah et al.
patent: 7037849 (2006-05-01), Chiu et al.
patent: 7138323 (2006-11-01), Kavalieros et al.
patent: 2006/0115972 (2006-06-01), Rotondaro et al.
patent: 2006/0121678 (2006-06-01), Brask et al.
patent: 2006/0166457 (2006-07-01), Liu et al.
patent: 2006/0183277 (2006-08-01), Brask et al.
patent: 2006/0244035 (2006-11-01), Bojarczuk, Jr. et al.
patent: 2007/0001241 (2007-01-01), Lim et al.

Affiliated with

Also associated with

Rating

Advanced high-k gate stack patterning and structure... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Advanced high-k gate stack patterning and structure..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Advanced high-k gate stack patterning and structure... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4201468