Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1999-06-09
2000-08-01
Fahmy, Wael
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257759, 257760, 438637, 438624, 438672, 438700, 438738, 438780, H01L 23485, H01L 214763
Patent
active
060970952
ABSTRACT:
The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material on the substrate and spaced apart metal contacts on the second dielectric. A space between adjacent metal contact side walls is filled with the second dielectric material. A ledge of a first dielectric material is on top of each second dielectric material filled space. The ledges are attached to adjacent side walls such that each ledge either fully spans the width of the filled space between adjacent side walls; or partially spans the width of the filled space between adjacent side walls, and the area between adjacent ledges is filled with second dielectric material. A top surface of each of the metal contacts, a top surface of the ledges and a top surface of any filled areas between adjacent ledges are at a common level. An additional layer of the second dielectric material is on at least some of the metal contacts, the ledges and optionally the filled areas between adjacent ledges. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of the metal contacts and optionally at least one of the ledges. The first and second dielectric materials have substantially different etch resistance properties.
REFERENCES:
patent: 5801095 (1998-09-01), Yew et al.
patent: 5886410 (1999-08-01), Chiang et al.
patent: 5935868 (1999-08-01), Fang et al.
"High Stud-to-Line Contact Area in Damascene Metal Processing"; IBM Technical Disclosure Bulletin, vol. 33, No. IA Jun. 1990.
Allied-Signal Inc.
Fahmy Wael
Lee Hsien-Ming
Weise Leslie A.
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