Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
2002-03-01
2003-12-02
Ngo, Hung V. (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S738000, C257S780000, C257S690000
Reexamination Certificate
active
06657124
ABSTRACT:
FIELD OF INVENTION
The present invention is related to an electronic package in general, and in particularly to an in-line process of PCB assembly with solder array joints.
BACKGROUND OF THE INVENTION
The package technology keeps on improving day by day, by using “light, thin, short and small” as design criteria in accordance with the application of tele/communication in the light of heat dissipation through dense array packages such as Ball Grid Array (BGA), Flip Chip and Chip Scale Package (CSP) are widely applied into commercial semiconductors. Following the matured wafer technology of Known Good Die (KGD), a kind of direct chip attachment technology makes array joints growing on the pads of dice to be installed onto the PCB. This has been regarded as the most dazzling “bright-star products” in the future according to packaging experts.
Nevertheless, there are existing some problems nowadays as listed in below:
1. The stand-off of the solder joints is too small to sustain the thermal stress which was generated from reflow process. The resolution so far is to fill with the underfill between dice and the substrate to reduce the induced thermal impacts as well as to increase the life times of solder joints.
2. The addition of underfill is a bottleneck to PCB assembly. Even, they are hard to repair after they had been filled with the underfill.
3. BGA also faces the reliability controversy resulted from insufficient stand-offs of solder joints. As the solder pitch keeps in getting smaller, the stand-off of a BGA, or a Flip Chip is proportionally reduced with the shrinkage of solder pitch, from regular 1.27 mm down to 0.8 mm or even goes below 0.5 mm.
4. As the wafer's manufacturing technology keeps on stepping forward, the design principle of “light, thin, short and small” can be achieved through the array solders that are implemented on a semiconductor die or on a BGA substrate. Still, under cost-effective consideration, the layers of PCB are not able to increase enough for functional purposes accordingly. In other words, the connections between a die and the corresponding PCB or a BGA substrate have to rely on their circuit layouts through the fanout of a BGA substrate or by PCB. At this moment, the connections between the die-pad and corresponding substrate-pad is almost in 1:1 volume ratio, thereby, there is no resolution for this problem.
To solve the bottleneck problems listed above, the inventions are connecting with conventional Surface Mount Technology (smt) and are illustrated by the followings.
OBJECTIVES AND SUMMARY OF THE INVENTION
The primary objective of present invention is to provide the reliable connections between a semiconductor die and the PCB by forming array joints on both of them so as to make the permanent connections after the reflow process has been completed. In this way, the stand-off of total solder joints can be increased with solid adhesions.
Secondly, the invention is to provide a method of increasing the shearing strengths of array joints that include two sets of melting points and the reflow temperature is between the aforesaid two melting points. The high melting solders are served as the pillars to maintain the stand-off, while, in the mean time, the rest of low melting solders will turn from the barrel-like shapes into the hourglass-like shapes that have better mechanical strengths, after the reflow temperature has been cooled down to room temperature. The high melting solder is defined that they are not melted or distorted at reflow stage while the low melting solders and solder pastes will be melted. The melting point of high melting solders is defined to have 20° C. higher than the reflow temperature, while the melting point of low melting solders is defined to have 20° C. lower than the reflow temperature of smt process.
Finally, the invention is also to provide a method of connecting the semiconductor die and PCB by using array solders with directional properties as to make permanent connections with fanout characteristic.
REFERENCES:
patent: 5598036 (1997-01-01), Ho
Ho Tony H.
Ngo Hung V.
Rosenberg , Klein & Lee
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