Advanced code error detection apparatus and system using maximal

Details Advanced code error detection apparatus and system using maximal Advanced code error detection apparatus and system using maximal

1992-07-06

1995-02-14

Canney, Vincent P.

Excavating

371 204, 371 682, G01R 3128

Patent

active

053901991

ABSTRACT:
A switching circuit switches operation states between a state in which m consecutive bit data of an M-sequence reception code having a period (2.sup.m -1), which is input to a measurement terminal, are set in a feedback shift register (FSR), and a state in which the FSR is set in a closed-loop state to be set in a self-running state. A synchronization detection comparator sequentially compares each bit data output from the FSR in a self-running state with corresponding bit data of the reception code. On the basis-of the comparison result from the synchronization detection comparator, a control section determines that the bit data output from the FSR are a reference code, or outputs a command to the FSR through the switching circuit to fetch the m bit data again. A storage circuit stores consecutive bit data of the reception code which are input before the control section determines that the bit data are the reference code, and outputs the stored bit data upon delaying them by a predetermined period of time. A bit error detection comparator sequentially compares the bit data of the delayed reception code output from the storage circuit with the bit data output from the FSR and determined as the reference code.

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