Advanced BEOL interconnect structures with low-k PE CVD cap...

Details Advanced BEOL interconnect structures with low-k PE CVD cap... Advanced BEOL interconnect structures with low-k PE CVD cap...

2002-01-15

2004-05-18

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S637000, C257S640000, C257S642000, C257S759000, C257S762000

Reexamination Certificate

active

06737747

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the manufacture of high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices. More particularly, this invention relates to advanced back-end-of-line (BEOL) metallization structures for semiconductor devices using low-k dielectric materials. The invention is specifically directed to an advanced BEOL interconnect structure having a low-k cap layer, and a method of forming the interconnect structure using a plasma-enhanced chemical vapor deposition (PE CVD) process to form the cap layer.
BACKGROUND OF THE INVENTION
In semiconductor devices, aluminum and aluminum alloys have been used as the traditional interconnect metallurgies. While aluminum-based metallurgies have been the material of choice for use as metal interconnects over the past years, concern now exists as to whether aluminum will meet the demands required as circuit density and speeds for semiconductor devices increase. Because of these growing concerns, other materials have been investigated as possible replacements for aluminum-based metallurgies.
One highly advantageous material now being considered as a potential replacement for aluminum metallurgies is copper, because of its lower susceptibility to electromigration failure as compared to aluminum, as well as its lower resistivity.
Despite these advantages, copper suffers from an important disadvantage. Copper readily diffuses into the surrounding dielectric material during subsequent processing steps. To inhibit the diffusion of copper, copper interconnects are often capped with a protective barrier layer. One method of capping involves the use of a conductive barrier layer of tantalum, titanium or tungsten, in pure or alloy form, along the sidewalls and bottom of the copper interconnection. To cap the upper surface of the copper interconnection, a dielectric material such as silicon nitride is typically employed.
For example, state-of-the-art dual damascene interconnect structures comprising copper interconnects are described in “A High Performance 0.13 &mgr;m Copper BEOL Technology with Low-k Dielectric,” by R. D. Goldblatt et al., Proceedings of the IEEE 2000 International Interconnect Technology Conference, pp. 261-263. A typical interconnect structure using low-k dielectric material and copper interconnects is shown in FIG.
1
. The interconnect structure comprises a lower substrate
10
which may contain logic circuit elements such as transistors. A dielectric layer
12
, commonly known as an inter-layer dielectric (ILD), overlies the substrate
10
. In advanced interconnect structures, ILD layer
12
is preferably a low-k polymeric thermoset material such as SiLK™ (an aromatic hydrocarbon thermosetting polymer available from The Dow Chemical Company). An adhesion promoter layer
11
may be disposed between the substrate
10
and ILD layer
12
. A layer of silicon nitride
13
may be disposed on ILD layer
12
. Silicon nitride layer
13
is commonly known as a hardmask layer or polish stop layer. At least one conductor
15
is embedded in ILD layer
12
. Conductor
15
is typically copper in advanced interconnect structures, but may alternatively be aluminum or other conductive material. A diffusion barrier liner
14
may be disposed between ILD layer
12
and conductor
15
. Diffusion barrier liner
14
is typically comprised of tantalum, titanium, tungsten or nitrides of these metals. The top surface of conductor
15
is made coplanar with the top surface of silicon nitride layer
13
, usually by a chemical-mechanical polish (CMP) step. A cap layer
17
, also typically of silicon nitride, is disposed on conductor
15
and silicon nitride layer
13
. Silicon nitride cap layer
17
acts as a diffusion barrier to prevent diffusion of copper from conductor
15
into the surrounding dielectric material.
A first interconnect level is defined by adhesion promoter layer
11
, ILD layer
12
, silicon nitride layer
13
, diffusion barrier liner
14
, conductor
15
, and cap layer
17
in the interconnect structure shown in
FIG. 1. A
second interconnect level, shown above the first interconnect level in
FIG. 1
, includes adhesion promoter layer
18
, ILD layer
19
, silicon nitride layer
20
, diffusion barrier liner
21
, conductor
22
, and cap layer
24
.
The first and second interconnect levels may be formed by conventional damascene processes. For example, formation of the second interconnect level begins with deposition of adhesion promoter layer
18
. Next, the ILD material
19
is deposited onto adhesion promoter layer
18
. If the ILD material is a low-k polymeric thermoset material such as SiLK™, the ILD material is typically spin-applied, given a post apply hot bake to remove solvent, and cured at elevated temperature. Next, silicon nitride layer
20
is deposited on the ILD. Silicon nitride layer
20
, also known as a hardmask layer or polish stop layer, is patterned by conventional photolithography techniques, and then acts as a mask during subsequent etching of ILD layer
19
, adhesion promoter layer
18
and cap layer
17
, to form at least one trench and via. The trenches and vias are typically lined with diffusion barrier liner
21
. The trenches and vias are then filled with a metal such as copper to form conductor
22
in a conventional dual damascene process. Excess metal is removed by a CMP process. Silicon nitride layer
20
acts as a polish stop layer during the CMP process. Finally, silicon nitride cap layer
24
is deposited on copper conductor
22
and silicon nitride layer
20
.
Silicon nitride layers
13
and
20
are not necessary components of the finished interconnect structure, because after planarization by CMP, dielectric cap layers
17
and
24
are deposited across copper conductors
15
and
22
, and ILD layers
12
and
19
. In fact, hardmask or polish stop layers
13
and
20
are often polished away completely in at least some portions of the wafer, prior to dielectric cap layer deposition.
Due to the need for low temperature processing after copper deposition, the cap layers
17
and
24
are typically deposited at temperatures below 450° C. Accordingly, cap layer deposition is typically performed using plasma enhanced chemical vapor deposition (PE CVD) or high density plasma chemical vapor deposition (HDP CVD) wherein the deposition temperature generally ranges from about 200° C. to about 500° C.
PE CVD and HDP CVD silicon nitride have been used for many other applications in semiconductor device manufacturing. However, in using a silicon nitride cap for copper interconnects, conventional PE CVD silicon nitride creates reliability problems. In particular, silicon nitride films deposited using conventional PE CVD processes generally exhibit poor adhesion to the copper surface. For instance, some nitride films delaminate and form blisters over patterned copper lines, particularly during subsequent dielectric depositions, metallization, and chemical-mechanical polishing. After being deposited onto copper metallurgy, additional insulating layers generally will be deposited over the silicon nitride film. However, subsequent deposition of insulating layers onto the nitride film will produce stress which can cause the silicon nitride film to peel from the copper surface. This delamination results in several catastrophic failure mechanisms, including lifting intermetal dielectrics, lifting copper lines, and copper diffusion from uncapped copper lines. Such results are generally seen in dual damascene processing wherein delamination of the silicon nitride hardmask layer generally occurs during copper chemical-mechanical polishing (CMP).
Silicon nitride films deposited using HDP CVD generally exhibit superior adhesion to copper surfaces as compared to PE CVD silicon nitride films. However, HDP CVD silicon nitride films are more costly to produce than PE CVD silicon nitride films. Moreover, significant disadvantages occur when HDP CVD silicon nitride films are used in advanced ground-rule inte

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