Fishing – trapping – and vermin destroying
Patent
1994-06-14
1996-09-17
Picardat, Kevin M.
Fishing, trapping, and vermin destroying
437214, 437217, 437219, 437220, H01L 2160
Patent
active
055568076
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of electronic packaging, particularly a method and resulting structure for a high speed chip carrier.
2. Description of Related Art
High speed computers typically require minimal inductance between the signal lines that link the integrated circuits (ICs) of the system. The ICs are usually mounted into chip carriers which have a plurality of leads that interconnect the chips and the signal lines. The leads are typically parallel, which creates an unacceptable amount of inductance between the leads, particularly between the power and signal lines. This problem becomes greater as the speed of the system increases.
U.S. Pat. Nos. 4,891,687 and 4,835,120 issued to Mallik et al, discloses an IC package that has a pair of copper plates bonded to the lead frame of the package. The copper planes are separated by insulative material and have tabs that are connected to designated leads of the lead frame. The power and ground pins of the IC are attached to each conductive plate respectively. Power flows into the package, from the leads, through the plates and into the IC. The creation of separate power and ground planes eliminates the parallelism between the leads, which reduces the inductance and increases the capacitance of the signal lines. This reduction in impedance is particularly important for high speed circuitry.
Although the dual plane package reduces the noise within the lines, the specific inductance and capacitance values are somewhat unpredictable because of the size and tolerances associated with the plates. Furthermore, there is no way of connecting passive components to the lead frame to customize the package. It would therefore be desirable to have an IC package that would allow the designer to control the impedance and noise of the circuit within the package. It would also be desirable to have a method of constructing an IC package that can provide internal routing with the package.
SUMMARY OF THE INVENTION
The present invention is a method and resulting structure for constructing an IC package utilizing thin film technology. The package has a bottom conductive plate that has a layer of ceramic vapor deposited onto the plate in a predetermined pattern. Adjacent to the insulative layer of ceramic is a layer of conductive metal vapor deposited onto the ceramic. The layer of metal can be laid down onto the ceramic in a predetermined pattern to create a power plane, a plurality of signal lines, or a combination of power planes and signal lines. On top of the layer of conductive material is a lead frame separated by a layer of insulative polyimide material. The polyimide material has a plurality of holes filled with a conductive material, which electrically couple the layer of vapor deposited conductive material with the leads of the lead frame. The power and ground pads of the IC are attached to the layer of conductive material and conductive plate, which are also coupled to corresponding leads of the lead frame, thereby connecting the IC to the leads of the lead frame. The signal pads of the IC are connected to the lead frame and/or signal lines formed within the layer of vapor deposited conductive material. The IC and attached circuit package can then be encapsulated in a plastic shell as is known in the art. The use of a thin film layer of insulative oxide material not only reduces the thickness of the package, but increases the dielectric constant and resulting capacitance of the circuit as well.
Additionally, resistive or capacitive material can be vapor deposited onto or between the signal lines of the conductive layer, wherein resistors and capacitors are attached to the individual lines. The inclusion of resistors and capacitors into the package provides a customized controlled line impedance over packages known in the art. The present invention also allows the creation of multiple layers and routing within the package, which is beneficial for packages with two or more ICs. The external routing w
REFERENCES:
patent: 4835120 (1989-05-01), Mallik et al.
patent: 4891687 (1990-01-01), Mallik et al.
patent: 4949163 (1990-08-01), Sudo et al.
patent: 4987100 (1991-01-01), McBride et al.
patent: 5206188 (1993-04-01), Hiroi et al.
patent: 5235209 (1993-08-01), Shimizu et al.
patent: 5243496 (1993-09-01), Mermet-Guyennet
Ban Syunsuke
Bhattacharyya Bidyut K.
Mallik Debendra
Takikawa Takatoshi
Yamanaka Shosaku
Intel Corporation
Picardat Kevin M.
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