ADSL transceiver implemented with associated bit and energy load

Pulse or digital communications – Transceivers – Transmission interface between two stations or terminals

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375260, 375225, 375222, H04B 138

Patent

active

060849061

ABSTRACT:
An ADSL transceiver includes a new circuit and various iterative initialization and fine tuning routines for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal. The routines quickly converge to a target data rate by first estimating a power margin, and generating a bounded interval that includes the target rate. Thereafter, a binary iterative portion of the routine takes over and effectuates a final convergence to the target rate. A new mechanism for determining useful sub-channels is also disclosed. The resulting routines are extremely useful in that they maximize a data rate for a given power margin, and conversely, maximize a power margin for a given data rate. Two variants of a fine tuning process are also disclosed, and both can be used in combination to maximize system performance. The circuits and routines are preferably implemented in the form of an integrated circuit or module that includes a digital signal processor (DSP) and associated memory running a permanent binary coded executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. In an alternative form, the DSP may include a RAM that is loaded with the initialization and fine tuning routines from a computer readable media such as a floppy disk, a hard disk, a magnetic tape, a CD-ROM or other non-volatile computer readable storage media. In another embodiment, the circuits and routines may be implemented in the form of a software modem operating directly on a user's machine instead of using a separate DSP and associated memory.

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