Adjustment of divided clock in disk head read circuit

Details Adjustment of divided clock in disk head read circuit Adjustment of divided clock in disk head read circuit

2011-03-08

2011-03-08

Negrón, Daniell L (Department: 2627)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

Reexamination Certificate

active

07903359

ABSTRACT:
A read circuit for providing multi-bit disk data to a disk controller in correspondence to analog data from a disk head, includes a low frequency clock generator whose phase is adjustable in response to a detection of the synchronization marker in the analog disk data. A high frequency clock is phase-locked to the output of the disk head, and synchronizes operation of an A/D converter and a bit detector which produces a verified single-bit based on the A/D output. A serial-to-parallel converter converts the single bit output from the bit detector to a parallel output, and the parallel output is latched to multi-bit disk data for use by the disk controller in accordance with a low frequency clock. The low frequency clock is generated by a clock generator from the high frequency clock with a phase that is adjustable in response to the synchronization mark detector.

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