Adjustment of avalanche voltage in DIFMOS memory devices by cont

Details Adjustment of avalanche voltage in DIFMOS memory devices by cont Adjustment of avalanche voltage in DIFMOS memory devices by cont

1977-01-10

1979-01-02

Dost, Gerald A.

Metal working

Method of mechanical manufacture

Assembling or joining

148 15, 148187, B01J 1700

Patent

active

041319834

ABSTRACT:
A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

REFERENCES:
patent: 3881180 (1975-04-01), Gosney

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