Adjustment of avalanche voltage in DIFMOS memory devices by cont

Details Adjustment of avalanche voltage in DIFMOS memory devices by cont Adjustment of avalanche voltage in DIFMOS memory devices by cont

1975-12-29

1977-07-12

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 41, 357 54, 357 13, 357 91, 307304, H01L 2978, H01L 2702, H01L 2990, H01L 2934

Patent

active

040358208

ABSTRACT:
A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

REFERENCES:
patent: 3740731 (1973-06-01), Ohwada et al.
patent: 3868187 (1975-02-01), Masuoka
patent: 3882469 (1975-05-01), Gosney
patent: 3886582 (1975-05-01), Kobayashi et al.
patent: 3906296 (1975-09-01), Maserjian
IBM Technical Disclosure Bulletin; by Young; vol. 17, No. 4, Sept. 1974, pp. 1208 and 1209.

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