Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
2011-03-01
2011-03-01
Payne, David C (Department: 2611)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
Reexamination Certificate
active
07899143
ABSTRACT:
An apparatus for adjusting a lockout time in a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock and generates adjusted and encoded vectors, both indicating a first time period. A select vector is employed to select a delayed version of the reference clock that lags the reference clock by a second time period, which is slightly less than a number of reference clock cycles. The select vector is reduced in value to generate the adjusted vector. The receivers are coupled to the delay-locked loop. Each of the one or more receivers receives the encoded vector and a corresponding strobe, and locks out reception of the corresponding strobe for the first time period following transition of the corresponding strobe. The encoded vector is employed to determine the first time period by selecting a delayed version of the corresponding strobe.
REFERENCES:
patent: 6025744 (2000-02-01), Bertolet et al.
patent: 6307877 (2001-10-01), Philips et al.
patent: 6377097 (2002-04-01), Shuler, Jr.
patent: 6433600 (2002-08-01), Ilkbahar
patent: 6505262 (2003-01-01), Kurd et al.
patent: 6697420 (2004-02-01), Simon et al.
patent: 6804800 (2004-10-01), Rodriguez
patent: 6832325 (2004-12-01), Liu
patent: 7003686 (2006-02-01), Chua-Eoan et al.
patent: 7271634 (2007-09-01), Daga et al.
patent: 7280417 (2007-10-01), Choi et al.
patent: 7283380 (2007-10-01), Srinivasan et al.
patent: 7453297 (2008-11-01), Kaviani
patent: 2002/0087911 (2002-07-01), Liu
patent: 2003/0217303 (2003-11-01), Chua-Eoan et al.
patent: 2004/0113654 (2004-06-01), Lundberg
patent: 2007/0001724 (2007-01-01), Na
patent: 2007/0136619 (2007-06-01), Chen et al.
patent: 2007/0217559 (2007-09-01), Stott et al.
patent: 2008/0013663 (2008-01-01), Cornelius et al.
Park, Joonbae et al. “A Semi-digital Delay Locked Loop for Clock Skew Minimization.” Proceedings Twelfth International Conference on VLSI Design. 1999. Publicaiton Date: Jan. 7-10, 1999. On pp. 584-588. Meeting Date Jan. 7, 1999-Jan. 10, 1999 Location: Goa, India.
Yamaoto, Kazuhiro et al. “Multi Strobe Circuit for 2.133 GHz Memory Test System.” Test Conference, 2006. ITC '06. IEEE International Oct. 2006, pp. 1-9.
Wang et al. “All-Digital Delay-Locked Loop/Pulsewidth-Control Loop with Adjustable Duty Cycles.” IEEE Journal of Solid-State Circuits. V. 41, No. 6. Jun. 2006.
“A Semi-Digital Delay Locked Loop for Clock Skey Minimization.” (undated), downloaded from IEEE Xplore on Nov. 19, 2008.
Huffman James W.
Huffman Richard K.
Payne David C
Shah Tanmay K
VIA Technologies Inc.
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