Adjusting threshold voltages by diffusion through refractory met

Details Adjusting threshold voltages by diffusion through refractory met Adjusting threshold voltages by diffusion through refractory met

1987-10-19

1988-11-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 56, 437162, 437200, 148DIG147, H01L 21225

Patent

active

047866110

ABSTRACT:
Adjusting field effect transistor (FET) threshold voltage (V.sub.T) by diffusing impurities in polysilicon gates through a refractory metal silicide. Dopants of different conductivities may be cross-diffused. This adjustment can be made relatively late in the fabrication of the wafers to provide a quick turn around time of custom circuits, gate arrays and application specific integrated circuits (ASICs). A masking step selectively provides blocking elements to prevent the diffusion from occurring in certain of the FETs.

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S. M. Sze, VLSI Technology, McGraw Hill, 1983, pp. 468-470.
L. C. Parrillo et al., "A Fine-Line CMOS Technology that Uses P.sup.+ Polysilcon/Silicide Gates for NMOS and PMOS Devices," IEDM Technical Digest, 1984, pp. 418-421.
James R. Pfiester et al., "E/D CMOS--A High Speed VLSI Technology," 1983 Symposium on VLSI Technology: Digest of Technical Papers, 1983, pp. 44-45.

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