Patent
1996-01-26
1998-02-10
Swann, Tod R.
395250, G06F 1300
Patent
active
057179000
ABSTRACT:
A computer network is connected via dual system busses to multiple digital modules such as a Central Processing Module with a Central Processor and also to a main memory module, plus an I/O module in addition to other possible modules, such as other Central Processing Modules. The Central Processor has a cache memory which is accessed on the basis of adjustable priorities, the most normal situation being that the Central Processor has first priority to cache access. However, under certain other conditions, the priority of access to cache is adjusted to give priority to an invalidation queue when it is almost full of invalidation addresses to be processed on invalidation cycles to the cache memory. Another priority is given to the invalidation queue after a Read-Lock operator is initiated by the processor. The resulting adjustable priorities work to optimize the integrity and speed of throughput of the system.
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Chow Christopher S.
Kozak Alfred W.
Petersen Steven R.
Starr Mark T.
Swann Tod R.
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