Adjusting delay circuitry

Details Adjusting delay circuitry Adjusting delay circuitry

1990-11-19

1992-05-05

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307606, 307597, 328 55, 328 66, H03K 513, H03K 5159, H03K 301

Patent

active

051110865

ABSTRACT:
Gate speed evaluation circuitry evaluates the operating speed of gates of a calibration network and adjusts the length of a tapped delay network on the same chip to provide uniform delay in a signal.

REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 4859954 (1989-08-01), Yoshimura
Patent Abstract of Japan, vol. 7, No. 4 (E-151) (1149) Jan. 8, 1983 & JP-A-57 162 835 (Fijitsu, K.K.) Oct. 6, 1982.
Patent Abstract of Japan, vol. 9, No. 178 (E-330) (1902) Jul. 23, 1985 & JP-A-60 47 517 (Hitachi Seisakusho KK) Mar. 14, 1985.
NTIS Tech Notes, Jan. 1989, Springfield, VA, U.S., p. 19; Ansell E.: "System measures logic-Gate delays', " See whole document.
Patent Abstracts of Japan, vol. 10, No. 283 (E-440) (2339) Sep. 26, 1986 & JP-A-61 101 117 (Hitachi Micro Comput Eng Ltd.) May 20, 1986, see whole document.

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