Adjusting circuit and method for delay circuit

Details Adjusting circuit and method for delay circuit Adjusting circuit and method for delay circuit

2007-05-17

2009-10-20

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S161000

Reexamination Certificate

active

07605629

ABSTRACT:
Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals, and the adjusting circuit includes: a difference signal generating circuit, for generating a plurality of difference signals according to a reference clock signal and the delay clock signals; a delay processing circuit, coupled to the difference signal generating circuit, for determining the target delay clock signal by computing a corresponding number of delay units for a specific phase of the reference clock signal according to the difference signals; wherein the target delay clock signal is one of the delay clock signals.

REFERENCES:
patent: 6404833 (2002-06-01), Takebe
patent: 6518807 (2003-02-01), Cho
patent: 6940768 (2005-09-01), Dahlberg
patent: 6950487 (2005-09-01), Lin
patent: 2001/0050581 (2001-12-01), Saeki
patent: 2005/0127964 (2005-06-01), Lee

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