Adjustble gain signal processing device

Details Adjustble gain signal processing device Adjustble gain signal processing device

2011-04-12

2011-04-12

Nguyen, Khai M (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Nonlinear

C341S143000, C330S010000, C330S251000

Reexamination Certificate

active

07924190

ABSTRACT:
A CLK generating section of a digital ALC generates a multiplication clock signal that is obtained by multiplying a triangular wave generated at a triangular wave generating circuit. On the basis of the multiplication clock signal, a signal converting section converts a one-bit digital audio signal outputted from an outputting stage into a multi-bit digital signal, and monitors a voltage value of an input signal. A level controlling section controls a voltage level on the basis of a target level inputted from an exterior of an LSI. On the basis of a control signal inputted from an exterior of the LSI, a volume controlling section outputs, to a PGA, a gain adjusting signal so as to vary a waveform of an input signal.

REFERENCES:
patent: 5815581 (1998-09-01), Andersson
patent: 5917369 (1999-06-01), Nguyen
patent: 6339360 (2002-01-01), Santillano
patent: 6897725 (2005-05-01), Honda
patent: 7151404 (2006-12-01), Lee et al.
patent: 2008-017367 (2008-01-01), None
patent: 2010-073213 (2010-04-01), None
patent: 2010-081189 (2010-04-01), None

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