Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-11-08
2003-12-09
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C156S345240, C156S345510, C438S009000, C438S694000
Reexamination Certificate
active
06660651
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to an adjustable wafer stage, and a method and system for performing process operations using same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor
10
, as shown in
FIG. 1
, may be formed above a surface
15
of a semiconducting substrate or wafer
11
comprised of doped-silicon. The substrate
11
may be doped with either N-type or P-type dopant materials. The transistor
10
may have a doped polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
of the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown).
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor
10
depicted in
FIG. 1
, are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, metals, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes, along with various ion implant and heating processes, are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in
FIG. 1
, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed with a high degree of accuracy due to the reduced size of those features in such modern devices. For example, gate electrodes may now be patterned to a width
12
that is approximately 0.18 &mgr;m (1800 Å), and further reductions are planned in the future. The width
12
of the gate electrode
14
corresponds approximately to the channel length
13
of the transistor
10
when it is operational. Of course, the critical dimension
12
of the gate electrode
14
is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for a method that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, e.g., to form the gate electrode
14
to its desired critical dimension
12
.
In manufacturing semiconductor devices, many deposition processes and etching processes may be performed. For example, a variety of process layers, e.g., layers of polysilicon, metal or insulating materials, may be formed by performing a variety of deposition processes, e.g., chemical vapor deposition (“CVD”), plasma enhanced chemical vapor deposition (“PECVD”), physical vapor deposition (“PVD”), etc. Additionally, a variety of etching processes, such as a dry plasma etching process, may be performed to pattern an underlying process layer.
Unfortunately, many processes used in manufacturing integrated circuit devices, such as deposition and etch processes, tend to exhibit across-wafer variations. For example, a deposition process may tend to produce process layers that are thicker near an edge region of the wafer than near a center region of the wafer, and vice versa. Moreover, this variation may not be uniform around the circumference of the wafer, i.e., the thickness variation may occur in only one quadrant of the wafer. Similarly, etching processes may exhibit across-wafer non-uniformity characteristics. For example, the etching rate may be greater near a center region of the wafer than it is near an edge region of the wafer. Moreover, as with deposition processes, these variations may not be uniform around the circumference of the wafer, i.e., they may occur in localized areas.
Such variations are problematic in modem integrated circuit manufacturing. Such variations, even if small in absolute magnitude, may adversely impact the ability to form features on integrated circuits with the precision required for modem integrated circuit devices. Additionally, such process variations may require adjustments to subsequent processing operations in an attempt to compensate for the across-wafer variations. For example, a deposition process may result in a process layer that is thicker at the edge of the wafer than it is at the center of the wafer, i.e., the process layer may have a surface profile that is approximately concave. In that situation, a subsequent chemical mechanical polishing (“CMP”) process may be performed in which parameters of the CMP process are adjusted in an effort to increase the polishing performed near the edge region of the wafer. Accordingly, such across-wafer variations resulting from certain processing operations are undesirable.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems described above.
SUMMARY OF THE INVENTION
The present invention is generally directed to a process tool comprised of an adjustable wafer stage, and various methods and systems for performing process operations using same. In one illustrative embodiment, the process tool is comprised of a process chamber, and an adjustable wafer stage positioned in the process chamber to receive a wafer positioned thereabove, the wafer stage having a surface that is adapted to be raised, lowered or tilted. In further embodiments, the process tool may be comprised of a plurality of pneumatic cylinders or rack and pinion combinations that are operatively coupled to the wafer stage. The cylinders and rack and pinion combinations may be used to move or adjust the wafer stage. In even further embodiments, the
Advanced Micro Devices , Inc.
Powell William A.
Williams Morgan & Amerson P.C.
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