Static information storage and retrieval – Floating gate – Particular biasing
Patent
1993-12-01
1996-05-28
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518502, 36518524, 36518529, G11C 1134
Patent
active
055218679
ABSTRACT:
A flash EPROM circuit for providing a tight erase threshold voltage distribution. The circuit includes an array of memory cells having gates, sources and drains. Bit lines are coupled to the drains of a column of cells in the memory array. A plurality of word lines are each coupled to the gates of a row of cells in the memory array. A first voltage source is coupled to the bit lines to converge threshold voltages of erased memory cells. A second voltage source is coupled to the word lines to control the threshold voltages of the erased memory cells.
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Haddad et al., "An Investigation of Erase-Mode Dependent Hole Trapping in Flash EEPROM Memory cell", Nov. 1990, vol. 11, IEEE pp. 514-516.
Haddad et al., "Degradations due to Hole Trapping in Flash Memory cells", Mar. 1989, vol. 10, IEEE, pp. 117-119.
Chen Jian
Cleveland Lee E.
Hollmer Shane
Kwan Ming-Sang
Liu David
Advanced Micro Devices , Inc.
Hoang Huan
Nelms David C.
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