Coded data generation or conversion – Digital code to digital code converters – Parallel to serial
Utility Patent
1998-09-23
2001-01-02
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Parallel to serial
C341S100000
Utility Patent
active
06169501
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of data transmission, and more particularly, to converting data between serial and parallel formats. Shift registers may be employed for converting the data format and tracking the status of the conversion.
DESCRIPTION OF THE RELATED ART
Asynchronous serial digital transmission is a common form for transferring information in the telecommunication industry. A device that is receiving an asynchronous stream of data must sample the data stream at times when the data is stable in order to guarantee accurate reception of the data stream. A typical receiving device may use an internal sampling clock to sample the serial data stream. However, an asynchronous serial data stream is, by its nature, asynchronous to the internal sampling clock. Therefore, if the data stream is simply sampled on edges of the internal clock, the receiving device may not be assured that each time data is sampled, correct data will be received. This is because even though the frequency of the internal clock may be the same as the data stream transmission rate, the phase between the sampling clock and the data stream may drift so that clock edges of the sampling clock occur during times when data on the data stream is unstable. Therefore, it would be desirable for a device that is receiving an asynchronous stream of data to somehow synchronize its internal sampling clock to the incoming asynchronous data in such a way as to guarantee that the serial data is stable when it is sampled. Moreover, it is desirable that the synchronization process be done in a way such that data is not lost.
If the incoming serial data stream is well defined in terms of bit rate, transmission time, and threshold values, and this information is known to the receiving device, then the synchronization problem is simplified. However, the problems of synchronization are compounded if no assumptions can be made about the incoming serial data stream. For example, if a receiving device must be capable of receiving asynchronous data streams at different transmission rates, then the synchronization logic must be able to handle changes in the transmission rate. Traditional synchronization solutions such as a phase locked loops are ineffective for synchronizing to an asynchronous serial digital data stream. This is because a phase locked loop must synchronize to a periodic reference. However, an asynchronous digital data stream may not be periodic. For example, if the bit stream 10011 is transmitted, there is no transition edge in the data stream for two consecutive bit periods. The problem is exacerbated when long strings of zeros or ones are transmitted. Therefore, a traditional phase locked loop would not be able to maintain synchronization. Thus, it is desirable to have a receiving device for receiving an asynchronous data signal that samples the data signal at times when each bit is stable without missing any bits. To accomplish this, it would be desirable to be able to synchronize an internal sampling clock to an asynchronous data signal.
Furthermore, conventional phase locked loops may require several clock cycles to synchronize. Thus, data may be lost for the periods before synchronization is completed. Thus, it is desirable to shorten the amount of time required to synchronize. Preferably, synchronization (or phase locking) would occur immediately.
If the asynchronous data stream is a serial digital data stream, once the data is received it may be necessary to convert the data from a serial format to a parallel format. Also, if data is to be transmitted from the same device it may be necessary to convert parallel data into serial data for transmission. Similarly, if parallel data is received as the transmitted data, in some applications it may be desirable to convert to serial data and vice versa. Typically, a shift register is used to convert data from a serial format to a parallel format or from a parallel format to a serial format. Typically the shift register is of a fixed length and a counter is used to indicate when all the bits in the shift register have been shifted in or out. However, if the length of data words to be converted is not a fixed value then a conventional fixed length shift register and counter may not be used. Likewise, if the word length of the data must be dynamically altered, a fixed length shift register and counter are inappropriate. Furthermore, as the length of the word to be converted increases, so must the complexity of the counter used to track the status of the conversion. In high speed applications involving long data words the counter size may be prohibitive as to the speed at which the parallel-to-serial or serial-to-parallel converter may operate.
It would thus be desirable to have a general purpose serial-to-parallel or parallel-to-serial converter that provides the capability to convert the data format for variable word sizes. Also, it would be desirable for the data converter to scale with changes in the word size with negligible impact on performance.
Devices for receiving and/or transmitting serial data streams may often be implemented as custom circuit designs. However, when it becomes necessary to upgrade the device to a new process or new technology or to provide for faster transmission rates or different data formats, such custom designs may not scale well in terms of size and performance. A custom logic design that works for one type of semiconductor component, such as a gate array employing a certain process and operating frequency, may not operate if the process or operating frequency is changed. It would be desirable to have a design for sampling asynchronous data transmissions and converting the data stream from serial-to-parallel or parallel-to-serial formats where the design is easily scaled to different device processes operating speeds and architectures.
SUMMARY
Synchronization logic for synchronizing a sample clock to an asynchronous data sample is described. In one embodiment the synchronization logic may include a counter for measuring the time between a transition edge of the data on the asynchronous data signal and a sample edge of the sample clock. If the time between these two events is less than a dead-band value or if these two events occur concurrently, then a warning signal may be generated to indicate that the sample clock edge occurred too close to the data transition to ensure that the data sample will be valid. The warning signal may be used to readjust the phase of the sample clock so that sample transitions will occur during times when the data is stable on the asynchronous data signal.
Sample clock synchronization logic for sampling an asynchronous data signal may include a bit-rate counter which creates a terminal count clock signal that approximately matches the data rate frequency of the asynchronous data signal. A phase delay counter may be used to generate the sample clock signal at a phase delay from the terminal count clock signal provided by the bit-rate counter. An edge detector may be provided to determine when a transition occurs on the asynchronous data signal. The edge detector may provide an edge signal to glue logic to indicate when such a data transition has occurred. The glue logic may then cause the bit-rate counter and phase delay counter to be restarted so that the phase of the sample clock is readjusted. This will cause the sample clock edge to occur at approximately the phase delay count value from the edge of the data transition on the asynchronous data signal, thus assuring correct sampling.
The bit-rate counter may be programmable such that a bit-rate value is loaded into the bit-rate counter to select the frequency at which the terminal count clock signal will be generated. Also, a subtractor may be employed to subtract the count value of the bit-rate counter from the programmed bit-rate value. The difference from the subtractor may be compared to a dead-band value to determine if the sample clock transition will occur too close to an edge on the asynchronous data signal
Conley Rose & Tayon PC
Jean-Pierre Peguy
Kowert Robert C.
National Instruments Corp.
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