Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-10-22
2004-11-09
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S334000, C327S536000
Reexamination Certificate
active
06815998
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a circuit used to regulate the read-back voltage applied to address lines of a memory circuit during a read-back operation. More specifically, the present invention relates to a circuit that provides a read-back voltage as an adjustable percentage of a core supply voltage, with the ability to select the specific percentage depending on the actual level of the core supply voltage.
BACKGROUND OF THE INVENTION
Programmable logic devices, such as field programmable gate arrays (FPGAs), include configuration memory cells that are loaded with configuration data values. These configuration data values control the configuration of the programmable logic device. FPGAs often include a read-back mechanism that enables the previously written configuration data values to be read from the configuration memory cells.
FIG. 1
shows a conventional array of configuration memory cells (i.e., a configuration memory) such as used by Xilinx, Inc., assignee of the present invention. The configuration memory of
FIG. 1
is a 16-bit by 16-bit array, which includes 256 configuration memory cells. In general, each of the configuration memory cells is identified by a reference character M
X,Y
, where X and Y correspond with the row and column of the configuration memory cell. A typical array of configuration memory cells in a commercial device has on the order of 20,000 to one million memory cells. Thus the array of
FIG. 1
is much smaller than is typically used in a commercial embodiment, but nevertheless shows the structure of prior art configuration memories. To load the configuration memory, a bit stream of configuration data values (DATA) is shifted into data control circuit DC, under control of a clocking mechanism, until a frame of data (16 bits wide in this example) has been shifted into bit positions C
0
through C
15
of data control circuit DC. This frame of data is then routed from bit positions C
0
-C
15
to data lines D
0
-D
15
, respectively. Note that only data lines D
0
and D
15
are labeled for purposes of clarity.
Address control circuit AC, which includes address drivers
0
-
15
, drives a write enable signal onto one of the address lines A
0
-A
15
, thereby enabling the configuration data values on lines D
0
-D
15
to be written to a column of the configuration memory cells. Note that only address lines A
0
and A
15
are labeled for purposes of clarity.
Hsieh in U.S. Pat. No. 4,750,155 describes a five transistor memory cell that can be reliably read and written by applying a lower read-back voltage to a memory cell access transistor than is applied to the memory cell access transistor to write a new value. The Hsieh patent is incorporated herein by reference.
FIG. 2
is a circuit of a conventional six-transistor configuration memory cell M
0,0
that includes an n-channel access transistor T
1
, an n-channel reset transistor T
2
and two CMOS inverters I
1
and I
2
. As is well known in the CMOS design art, each of the two inverters I
1
and I
2
comprise one PMOS transistor and one NMOS transistor connected in series between the V
DD
supply voltage and ground. Inverters I
1
and I
2
are cross-coupled, thereby forming a latch. This latch is connected to data line D
0
by access transistor T
1
, which is controlled by a control voltage on address line A
0
. One or more lines Q and/or Q# extends from configuration memory cell M
0,0
to the FPGA logic structure (not shown) to control the configuration of this structure.
Configuration memory cell M
0,0
is initially reset by turning on the n-channel reset transistor T
2
. This reset mechanism enables the transistors in inverters I
1
and I
2
to be made relatively small (because configuration memory cell M
0,0
does not have to be reset via data line D
0
) While it is desirable to have relatively small transistors to reduce layout area, these small transistors undesirably result in relatively weak inverters I
1
and I
2
. Thus, the configuration memory value stored by inverters I
1
and I
2
is more susceptible to being disturbed during a read back operation where the charge on a large data line can flip the value stored by the small memory cell.
To write a configuration data value to the first column of configuration memory cells M
0,0
-M
15,0
, address driver
0
is controlled to drive a write enable voltage equal to the V
DD
supply voltage to address line A
0
. This relatively high write voltage assures that the access transistors (e.g., access transistor T
1
) are completely turned on during the write operation, such that the configuration data values are properly written to the configuration memory cells.
The configuration data values stored in configuration memory cells M
0,0
-M
15-15
can subsequently be read back to data control circuit DC on a column-by-column basis. For example, to read the configuration data values stored in the first column of configuration memory cells M
0,0
-M
15,0
, address control circuit AC causes address driver
0
to apply a read-back voltage to address line A
0
. This read-back voltage is typically selected to be equal to the V
DD
supply voltage minus the threshold voltage (V
T
) of access transistor T
1
. Under these conditions, the configuration data values stored in configuration memory cells M
0,0
to M
15,0
are read back to the data control circuit DC on data lines D
0
-D
15
. The read-back voltage is low enough to ensure that the read-back operation does not disturb the configuration data values stored in the configuration memory cells M
0,0
-M
15,0
. Note that the read-back voltage is referenced to the V
DD
supply voltage because the associated circuitry in data control circuit DC operates in response to the V
DD
supply voltage.
During normal operation, the V
DD
supply voltage can typically vary +/−10 percent with respect to a nominal supply voltage value. Thus, a V
DD
supply voltage having a nominal value of 1.2 Volts can vary from 1.08 to 1.32 Volts. For relatively low V
DD
supply voltages, the read-back voltage (V
DD
−V
T
) might be too low to reliably read the configuration memory cell. For example, a V
DD
supply voltage of 1.08 Volts would produce a read-back voltage of about 0.710 Volts, assuming a threshold voltage of 0.370 Volts. This read-back voltage may be inadequate to reliably read the configuration data values stored in the configuration memory cells.
It would therefore be desirable to have a method and apparatus for generating acceptable read-back voltages for a memory circuit, such as a configuration memory array of a programmable logic device, for all possible values of the V
DD
supply voltage.
SUMMARY
Accordingly, the present invention provides a read-back voltage generation circuit that provides a read-back voltage as an adjustable percentage of a supply voltage. The read-back voltage generation circuit has the ability to select the specific percentage depending on the actual level of the supply voltage. For example, if the supply voltage has a relatively high value, then the read-back voltage will be a relatively low percentage of the supply voltage. Conversely, if the supply voltage has a relatively low value, then the read-back voltage will be a relatively high percentage of the supply voltage. As a result, the read-back voltage will always be high enough to reliably read the configuration data values from the configuration memory cells within a given time margin, but not so high as to overwrite these configuration data values. The read-back voltage generation circuit is especially advantageous for use in a chip having a low core supply voltage, wherein a threshold voltage drop (V
T
) represents a large percentage of the core supply voltage.
In one embodiment, the read-back voltage generation circuit buffers the read-back voltage through a low output impedance buffer that is capable of supplying the proper voltage for the address lines on the chip. The read-back voltage generation circuit is designed to use minimal DC current, but is still able to charge the address lines quickly a
Cartier Lois D.
Cunningham Terry D.
Hoffman E. Eric
Xilinx , Inc.
Young Edel M.
LandOfFree
Adjustable-ratio global read-back voltage generator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Adjustable-ratio global read-back voltage generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adjustable-ratio global read-back voltage generator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3343082