Adjustable phase controlled clock and data recovery circuit

Details Adjustable phase controlled clock and data recovery circuit Adjustable phase controlled clock and data recovery circuit

2007-09-18

2007-09-18

Kim, Kevin (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C375S373000

Reexamination Certificate

active

10604177

ABSTRACT:
A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

REFERENCES:
patent: 5119399 (1992-06-01), Santos et al.
patent: 6097768 (2000-08-01), Janesch et al.
patent: 6211741 (2001-04-01), Dalmia
patent: 6480049 (2002-11-01), Boerstler et al.

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