Adjustable phase clock circuit using the same and related method

Details Adjustable phase clock circuit using the same and related method Adjustable phase clock circuit using the same and related method

1998-02-05

1999-11-23

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327156, 327158, H03L 700

Patent

active

059907134

ABSTRACT:
An adjustable phase clock includes a number (n) of delay circuits having respective controllable delays and being connected in cascade for generating n respective delayed signals. A first delay circuit receives the input clock signal and an nth delay circuit generates a total delay signal. A phase detector and filter are connected to the n delay circuits for controlling the respective delays thereof so that the total delay signal locks in relation to the input clock, such as to its period. In addition, the adjustable phase clock preferably further permits control of the output based upon selecting one of the n delayed signals having a corresponding adjusted phase delay relative to the input clock signal. Of course, multiple ones of the n delayed signals can also be selected. The adjustable phase clock may be used in a line locking application and an adjustable frequency clock circuit.

REFERENCES:
patent: 4389614 (1983-06-01), Staiger
patent: 4777385 (1988-10-01), Hartmeier
patent: 5050193 (1991-09-01), Ponsard
patent: 5119406 (1992-06-01), Kramer
patent: 5146121 (1992-09-01), Searles
patent: 5278457 (1994-01-01), Fujita et al.
patent: 5430394 (1995-07-01), Mcminn
patent: 5491673 (1996-02-01), Okayasu
patent: 5568078 (1996-10-01), Lee
patent: 5805003 (1998-09-01), Hsu

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