Adjustable frequency delay-locked loop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S159000, C327S161000

Reexamination Certificate

active

07109766

ABSTRACT:
A delay-locked loop300that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

REFERENCES:
patent: 4637018 (1987-01-01), Flora et al.
patent: 5712582 (1998-01-01), Yokota et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6353649 (2002-03-01), Bockleman et al.
patent: 6510191 (2003-01-01), Bockelman
patent: 6642800 (2003-11-01), Drapkin et al.
patent: 6891420 (2005-05-01), Martin et al.

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